1. 1.2.7 Trigger A.Nappi TB Nov 11, 2004

2. Digitizers (1.2.7.3)  Functions 25 MHZ 10 bit p.h. + 6bit time digitizers Digital processing  Flavor A: p.h. sum and mean time (groups of 2)  Flavor B: p.h. sum and minimum time (groups of 4)  Unsolved technical issues Analog signal shaping/preconditioning (ASIC) Individual delay adjustment  Evaluating alternative of WFD with special firmware  Caveat Assume analog summing in 2X6 groups for Shashlik and vetos. Cost not included Vetos not used for the trigger not costed

3. Routing/collector modules (1.2.7.4 to 7)  Module collector (PR-CAL-Veto) Sum and logical OR of signals from up to 2 digitizers (meant for x-y view in PR or strip grouping in CAL)  Strip routing (PR-CAL) Rearrange input data from digitizers grouped by module into outputs grouped by strip number  Strip collector (PR-CAL) Combine back to back strips and apply thresholds. Compute sums in depth  Technical issues Bandwidth requirements and interconnections Resync after zero suppression: latency and deadtime issues

4. Logic modules (1.2.7.8 to 11)  Projection card Clustering algorithm in projections  Pattern card Pattern recognition algorithm on logical strip signals  Boolean logic card Perform logic combinations of several inputs with programmable time windows  Technical issues Algorithms not yet defined. Complexity unknown

5. Service systems  Trigger supervisor (1.2.7.12) Realign partial trigger conditions Parallel trigger formation, enabling and prescaling Send trigger information to clock system for broadcast to front end electronics (F.E.E.)  Clock system (1.2.7.13) Master clock, phase locked to extraction RF or free running Clock drivers (fan out to subsystems) Clock receivers in F.E.E. crates

6. Other items  Infrastructure (1.2.7.14) Crates, cables, VME interfaces, readout interfaces, control PC’s Note: does not include racks (water cooled?)  Interconnection boards (1.2.7.2) Developed for test of intercommunication. Assume equipped with input and output memories to turn them into a general testing tool

7. PR-C X T-L PR-C Y T-L PR-C Y B-L PR-C X B-L PR-C X T-R PR-C Y T-R PR-C Y B-R PR-C X B-R PR-C strip coll PR- CAL logic UV, BV, CPV Veto coll More vetos Central logic Veto logic PR-C mod. coll. 1.2.7.3 Trigger digitizers flavor A flavor B 1.2.7.4, 1.2.7.5, 1.2.7.6 Route/collect modules module coll. strip routing strip coll. 1.2.7.8, 1.2.7.9, 1.2.7.10 Logic modules projection pattern boolean logic

8. Trigger Align, form, transmit, scalers 1.2.7.12 Trigger supervisor 1.2.7.13 Clock system Clock master+ drivers... + 100 receivers

9. Trigger summary (1.2.7.1) WBS #DescriptionPhys. m × y Eng. m × y Tech. m × y Equip. k$ Tot. k$...1Def. architecture1.210.26--37...2Interconn. boards0.170.480.3555161...3Digitizers1.773.411.956851386...4-7Routing/collectors2.082.612.34348981...8-11Logic modules1.642.071.64154632...12Trigger supervisor1.471.901.21130535...13Clock0.170.920.56385580...14Infrastructure--0.26520549...15-16Commissioning+LV31.510.35--49 Total k$ 1693 939 2277 4909

10. Time schedule: a first try  See notes on previous slide

11. Notes on time schedule  Assume 5 independent teams Note that none is available today  Definition of architecture preliminary to any hardware development For completion by end july 2005, estimate 2 FTE physicists + ½ FTE engineer  Trigger digitizers critical item Duration determined by task interdependency  Other durations and placements conditioned by digitizers (technical+resource dependencies) Design anticipated for early PDR Fabrication delayed for test with preproduced digitizers Clock system delayed due to arbitrary assumption that one engineer is shared between digitizer and clock development  Reconsider on the basis of WFD option and its time schedule