1. 12/7/2015 Paul Rubinov PRR Mar 2006 1 Production Readiness Review  Welcome!  Our motto: When you earnestly believe you can compensate for lack of talent by doubling your efforts, there’s not end to what you can’t do!

2. 12/7/2015 Paul Rubinov PRR Mar 2006 2 Outline  Answer charge #4  Answer #3 but not in the way you may have hoped  Answer charge #2  Address #5  Answer #6  Get your advice on #1

3. 12/7/2015 Paul Rubinov PRR Mar 2006 3 PRR history (spare)  A brief history of the AFE/TriP  The AFE was designed by John Anderson around the SIFT and SVX ASICs.  John was busy with other designs, so it fell to some of the rest of us to make sure this stuff worked.  See our motto  We got very nervous about making the SVX/SIFT work, especially at 132ns

4. 12/7/2015 Paul Rubinov PRR Mar 2006 4 PRR history  A brief history of the AFE/TriP  Abder was asked to design a new chip that would work at 132ns  Marvin proposed the basic idea based on lessons learned from SIFT/SVX MCM: 1. Keep the ASIC as simple as possible: use commercial ADCs, FPGAs, etc. The ASIC would have only what it must: front end Q amp, pipeline and discriminators. 2. Don’t try to pass fC level signals between different chip.

5. 12/7/2015 Paul Rubinov PRR Mar 2006 5 PRR history (spare)  Abder designed the Trigger and Pipeline chip by 3/2002!  We worked on designing a replacement MCM for existing boards, so we could avoid making new boards, but it became clear that new boards would be simpler/safer/cheaper  The 1 st AFEII TDR is from June 2002  Dzero lost interest because 132ns went away and John came back and made the AFE work (and GG and JW and MM and others)

6. 12/7/2015 Paul Rubinov PRR Mar 2006 6 PRR history  We (Juan and Bruce and I) kept pluging away at this because the TriP chip looked very nice in testing. We also had strong support from Marvin.  Our proposal for AFEII was opposed on 2 main grounds. 1. AFEIs work ok 2. We needed “crisp” physics case to get support from the collaboration/lab/DOE

7. 12/7/2015 Paul Rubinov PRR Mar 2006 7 PRR History  Therefore we worked to understand AFE1 problems as best we could. We identified 4 main issues: (D0 note 4500) 1. SVX saturation – this is a killer but requires very detailed understanding of the detector and MC. Not easy to see at low lumi with the real detector 2. Tick to tick variation – very easy to see, but not lumi dependent.

8. 12/7/2015 Paul Rubinov PRR Mar 2006 8 PRR History  We identified 4 main issues (cont.): 3. Discriminator to analog crosstalk – severe and getting worse. Well demonstrated and understood. 4. Channel to channel variation – same order as tick to tick variation.

9. 12/7/2015 Paul Rubinov PRR Mar 2006 9 PRR History 2. Tick to tick variation – very easy to see, 1pe=10 adc counts

10. 12/7/2015 Paul Rubinov PRR Mar 2006 10 PRR History 3. Discriminator to analog crosstalk – severe and getting worse

11. 12/7/2015 Paul Rubinov PRR Mar 2006 11 AFEII fix by design  “Fix by design” means  Understand the problem  Avoid the situation causing the problem 1. SVX saturation is caused by resetting the SVX only in the gaps (because reset is slow). Ask Abder to design a chip with a very fast (but gentle) reset. So reset every xing (at 132 ns!)

12. 12/7/2015 Paul Rubinov PRR Mar 2006 12 AFEII fix by design (cont) 2. Tick to tick variation is caused by resetting only once per gap. Killed to birds with one stone by resetting every xing! 3. Discriminator to analog crosstalk. This is caused by discriminators firing while small charges are being integrated by the SVX (we can even tell which discr steps on which analog line by looking at the layout!). We fix this by NOT firing discriminator drivers during the active gate.

13. 12/7/2015 Paul Rubinov PRR Mar 2006 13 AFEII fix by design (cont) 4. Channel to channel variation is caused by using only one digital threshold for 64 (128) imperfectly matched analog channels. Our solution is to digitize everything and process every channel individually- every channel has its own pedestal and its own threshold. So analog mismatch can not cause pedestal or threshold mismatch.

14. 12/7/2015 Paul Rubinov PRR Mar 2006 14 Will the AFEIIt fix the AFE1 problems? Q: Will the AFEIIt address the problems seen on AFE1? A:Yes! By design!  The question is what NEW problems the AFEII has and how we solve them.  Will the AFEII degrade any aspect of current detector performance?

15. 12/7/2015 Paul Rubinov PRR Mar 2006 15 AFE1 non-problems  AFE1’s are very reliable.  AFE1’s (currently, at 40Mhz) read out with a very low BER.  Both “grey cable” and LVDS links  AFE1’s have a stable calibration for all aspects –cryo, bias, threshold, peds.

16. 12/7/2015 Paul Rubinov PRR Mar 2006 16 AFEIIt vs AFE1  Due to shutdown schedule we will not be able to do thorough testing of AFEIIt with beam before going into production.  GG actually pointed this out to director when the shutdown schedule was discussed  Our solution:  Test as much as possible with beam.  Test as much as possible without beam on the platform.  Don’t install a particular flavor of AFEIIt boards in quantity until we know it works.

17. 12/7/2015 Paul Rubinov PRR Mar 2006 17 AFEIIt vs AFE1  Strategy to make sure we do no harm: 1. Get an AFEIIt into CFT stereo slot on platform before shutdown because this requires the least infrastructure and CFT stereo is very well understood. 2. Instrument CFT stereo first. Leverage that experience to understand CFT axial performance. 3. Leverage platform experience and the 4CC cryostat to understand PS performance. Bottom line: don’t install boards until sure they are not WORSE than AFE1s they replace.

18. 12/7/2015 Paul Rubinov PRR Mar 2006 18 AFEIIt vs AFE1  Strategy to make sure we do no harm: Requires that we be able to operate almost any mixture of AFE1s and AFEIIt’s in the same crate/sequencer, side by side, face to face.  This is what we call “plug compatible” and this was a design requirement.  Same data format as AFE1, but not necessarily the same download. They are very different boards! “Best is the enemy of good”

19. 12/7/2015 Paul Rubinov PRR Mar 2006 19 AFEIIt vs AFE1 A: We have a solid strategy which we are following to make sure that the AFEIIt will not degrade any aspect of the current detector performance. But this requires that we be able to operate a mixed system of AFEIIt and AFE1 in a transparent fashion. (except for downloads!)

20. 12/7/2015 Paul Rubinov PRR Mar 2006 20 AFEIIt + AFE1 = ♥ 7 Feb 06 AFEIIt # 6, prototype, inserted into stereo slot 2B0. Data taken: store 4631, runs 215086-215108 (during run 215085 timing was being adjusted). About 7 % of events have readout errors. 17 Feb 06 AFEIIt # 6, with new terminations, inserted into stereo slot 2B0. No readout errors. Data taken: store 4653, runs 215519-215534 (solenoid and toroid off during run 215533) store 4654, runs 215540-215558, SMT Sequencer off store 4658, runs 215596-215600 21 Feb 06 AFEII #12, pre-production, inserted into 2B0 Data taken: store 4664, 36x20 (pbars lost in transfer), runs 215635-215643

21. 12/7/2015 Paul Rubinov PRR Mar 2006 21 AFEIIt + AFE1 = ♥  The 1 st run with AFEIIt on platform revealed a readout problem we had not detected before!  No errors bench testing with SaSeq  No errors in Phase V  No errors in CTS with Seq  No errors on platform during calibration or LED injection  Data dependent errors with beam!

22. 12/7/2015 Paul Rubinov PRR Mar 2006 22 AFEIIt readout errors  Readout errors ~7% in SOME slots on the platform and only with DATA (not even LEDs)  Required a lot of work to understand  But we do understand!  We can cause errors without beam by special “random” firmware  Cross talk in grey cable – can fix by adding series resistors.  But adding series resistors reduces voltage swing very close to the minimum!

23. 12/7/2015 Paul Rubinov PRR Mar 2006 23 Problem understanding  The “knee” This is AFE 1c!

24. 12/7/2015 Paul Rubinov PRR Mar 2006 24 Problem understanding  The “cross talk in the middle of VSVX” This is AFEIIt

25. 12/7/2015 Paul Rubinov PRR Mar 2006 25 Problem understanding  The “cross talk in the middle of VSVX” This is AFE 1c!

26. 12/7/2015 Paul Rubinov PRR Mar 2006 26 Problem understanding  The “knee” This is #12 in 12B0

27. 12/7/2015 Paul Rubinov PRR Mar 2006 27 Problem understanding  The “knee” This is AFE 1c!

28. 12/7/2015 Paul Rubinov PRR Mar 2006 28 Problem understanding  I think we have an ok model that reproduces the salient features  Problems are caused by: cable, sharing grounds, RC termination

29. 12/7/2015 Paul Rubinov PRR Mar 2006 29 Problem understanding  The “knee”

30. 12/7/2015 Paul Rubinov PRR Mar 2006 30 Problem understanding  The “baseline shift”

31. 12/7/2015 Paul Rubinov PRR Mar 2006 31 Problem fixes  Remove the RC termination on the SEQ!

32. 12/7/2015 Paul Rubinov PRR Mar 2006 32 Problem fixes  The “baseline shift” is virtually solved

33. 12/7/2015 Paul Rubinov PRR Mar 2006 33 Problem fixes  The “knee” is much improved

34. 12/7/2015 Paul Rubinov PRR Mar 2006 34 New idea 12ma -240mV

35. 12/7/2015 Paul Rubinov PRR Mar 2006 35 1.Put in the “pull down bias”  Very small layout change 2.Change from ABT to ACT  Just BOM, no effort, small cost  Gives larger driver (closer to “rails”) 3.Optimize seq timing  Plug in delay 4.Reprogram seq to fix cross talk  This allows async running Final Fix

36. 12/7/2015 Paul Rubinov PRR Mar 2006 36 Final Fix No errors report in AFEIIt preproduction boards since the “Final Fix” AFEII in 5A0,2,4,6 20 March 06 Pre-production boards inserted in 9A 9A0 1 2 3 4 5 6 7 #12 #14 #18 #20 (afe1 588 543 496 473 484 463 610 477 ) AFEII in 9A0,2,4,6 16 March 06 Pre-production boards inserted in 9A 9A0 1 2 3 4 5 6 7 #12 #14 #18 #20 (afe1 452 527 580 575 542 453 592 485 ) AFEII in 4B0-4B7, 10 March 06 Pre-production boards inserted in 4B0-4B7 4B0 1 2 3 4 5 6 7 #20 #13 #18 #19 #12 #11 #14 #15 (afe1 560 503 612 505 554 511 494 529 ) No readout errors, however 4B2 disabled during tests because of problems with board #18 AFEII in 12B0, 12A4, 11B6, 2A4, 2A0, 12A0 March 2-3 06

37. 12/7/2015 Paul Rubinov PRR Mar 2006 37 Readout on the platform  Confident that this is DONE  But took a lot of time Q: What about other aspects of the boards? Will they operate as smoothly, reliably and safely as the current boards?

38. 12/7/2015 Paul Rubinov PRR Mar 2006 38 Other aspects of AFEIIt  Required for CFT stereo:  Good signal to noise  Downloads/Calibration  Bias  Cryo

39. 12/7/2015 Paul Rubinov PRR Mar 2006 39 LED Spectra: AFE1 AFEII JW@FTG, 2006Mar21

40. 12/7/2015 Paul Rubinov PRR Mar 2006 40 LED Spectra: AFE1 AFEII

41. 12/7/2015 Paul Rubinov PRR Mar 2006 41 Pedestals, triggering on all crossings AFE1 AFEII

42. 12/7/2015 Paul Rubinov PRR Mar 2006 42 Pedestals, triggering on clock tick 63 AFE1 AFEII

43. 12/7/2015 Paul Rubinov PRR Mar 2006 43 LEDs on, rms of pulse height vs VLPC pixel# AFEII #12 in 5A0 AFE1 AFEII

44. 12/7/2015 Paul Rubinov PRR Mar 2006 44 LEDs on, rms of pulse height distribution vs VLPC pixel # AFEII #14 in 5A2 AFE1 AFEII

45. 12/7/2015 Paul Rubinov PRR Mar 2006 45 LEDs on, rms of pulse height distribution vs VLPC pixel # AFEII #18 in 5A4 AFE1 AFEII

46. 12/7/2015 Paul Rubinov PRR Mar 2006 46 LEDs on, rms of pulse height distribution vs VLPC pixel # AFEII #20 in 5A6 AFE1 AFEII

47. 12/7/2015 Paul Rubinov PRR Mar 2006 47 Peds rms, 5A0,triggering on all crossings or triggering on clock tick 63 AFEII AFE1

48. 12/7/2015 Paul Rubinov PRR Mar 2006 48 Peds rms, 5A2, triggering on all crossings or triggering on clock tick 63 AFEII AFE1

49. 12/7/2015 Paul Rubinov PRR Mar 2006 49 Other aspects of AFEIIt  Required for CFT stereo:  Good signal to noise You bet! And the mapping is correct- same as AFE1  Downloads/Calibration  Bias  Cryo

50. 12/7/2015 Paul Rubinov PRR Mar 2006 50 Platform test of AFEIIt  Elog entry 486329

51. 12/7/2015 Paul Rubinov PRR Mar 2006 51 Platform test of AFEIIt

52. 12/7/2015 Paul Rubinov PRR Mar 2006 52 CFT gui  CFT gui works with AFEIIt, but needs to be made faster if we have many boards

53. 12/7/2015 Paul Rubinov PRR Mar 2006 53 Other aspects of AFEIIt  Required for CFT stereo:  Good signal to noise You bet!  Downloads/Calibration Done! (JW and DS)  Bias Seems fine. No calibration required for AFEIIt preprod boards.  Cryo

54. 12/7/2015 Paul Rubinov PRR Mar 2006 54 Cryo control works ~75 counts/ohm ~40 counts peak to peak noise

55. 12/7/2015 Paul Rubinov PRR Mar 2006 55 Other aspects of AFEIIt  Required for CFT stereo:  Good signal to noise You bet!  Downloads/Calibration Done! (JW and DS)  Bias Seems fine. No calibration required for AFEIIt preprod boards.  Cryo Seems fine also. (SG and RA)

56. 12/7/2015 Paul Rubinov PRR Mar 2006 56 Reliability  Only time will tell, but…  Pick very good vendors for PCB and assembly  Vendors (and we) got plenty of practice with these boards: 1. 20 prototype AFEII (not t!) designed by JA 2. 10 prototype AFEIIt 3. 16 preprod AFEIIt

57. 12/7/2015 Paul Rubinov PRR Mar 2006 57 Reliability  Of the 16 preproduction boards:  9/10 boards delivered first had 0 problems  1 board had a solder splash between pins on a TriP-t -> cleared it up, board ok.  Of those 10, 1 failed in service. Was found to be a loose solder joint. Now fixed.

58. 12/7/2015 Paul Rubinov PRR Mar 2006 58 Reliability  Of the 16 preproduction boards:  Of the last 6, 2 had one bad via each  1 board had two reversed LEDs installed; this same board had a cold solder joint on an FPGA.  1 board will not program - JTAG not working - investigating.  That's 6 out of 16 with problems. 4 in assembly, 2 in pcb mfg. We think these last boards were reworked by hand.

59. 12/7/2015 Paul Rubinov PRR Mar 2006 59 Safety AFEIIt draws a LOT less power than AFE1 (at least the way we operate it right now) Voltage Current Required per board Current per backplane (estimated) Current available from PS per backplane Power dissipation per AFE II board (rounded up) +5 Volts1.7 Amps14 Amps40 Amp10 Watts +5.5 Volts1.0 Amps8 Amps20 Amps 6 Watts ±12 Volts0.5 Amps4 Amps6 Amps 6 Watts +3.3 Volts2.5 Amps20 Amps40 Amps 9 Watts Total 31 Watts (~ 45W/ AFE1)

60. 12/7/2015 Paul Rubinov PRR Mar 2006 60 So its perfect? Well, no, I never said that. But: no green wires on the preprod boards, only stuffing/DNI errors We should not be afraid to make the changes we think will add value!

61. 12/7/2015 Paul Rubinov PRR Mar 2006 61 Not so perfect DNI mistakes – both LH/RH. 1.R358 not stuffed. Should be 0 ohms. 2.TS4 (PIC ISP header) not stuffed. Should be stuffed. 3.X1 socket installed. Should be soldered directly in to the board to avoid height clearance problems. 4.R97 resistor (part of the voltage watchdog divider for +5.5V) should be changed from 5.23K to 5.49K to allow better margins with the platform supplies (upper reset at 6.15V) DNI mistakes – LH/RH specific. DO NOT INSTALL ON RH BOARDS: 1.R339,D31,R338,D30. These are the LH bayonet ok LEDs 2.U172, U173, U174, TS19, R345, C133, R343, C1152. These are the LH JTAG components. They should not be stuffed on RH boards. 3.Fuse sockets for F1 to F5 since these are for LH boards.

62. 12/7/2015 Paul Rubinov PRR Mar 2006 62 Changes from pre production to production 1.Add the -12V pulldowns  Done: 8x R0805 1Kohm 2.Move up the “shield plate” to remove the small ridge under the backing bar  Done 3.Space out the 7-seg display holders a little  Done 4.Add protection resistors to PCF8574  Not done

63. 12/7/2015 Paul Rubinov PRR Mar 2006 63 PCF8574 can get -12V if… Shorting risk

64. 12/7/2015 Paul Rubinov PRR Mar 2006 64 -12V pulldowns

65. 12/7/2015 Paul Rubinov PRR Mar 2006 65 -12V pulldowns

66. 12/7/2015 Paul Rubinov PRR Mar 2006 66 -12V pulldowns

67. 12/7/2015 Paul Rubinov PRR Mar 2006 67 -12V pulldowns

68. 12/7/2015 Paul Rubinov PRR Mar 2006 68 7 seg LED

69. 12/7/2015 Paul Rubinov PRR Mar 2006 69 Shield bar