1. 3D integration and microelectronics in “AIDA-2” for H2020
Valerio Re
INFN
Sezione di Pavia
Università di Bergamo
Dipartimento di Ingegneria
AIDA H2020 open meeting, February 17, 2014
V. Re

2. HEP and microelectronics
Support for the application of advanced technologies in view of the very demanding specifications of future HEP detector systems.
In the past decades, high-energy physics has taken a great benefit from advances in integrated circuit technology and interconnections for sensor readout.
For the HEP community to continue exploiting industrial advances in these fields, a network of physicists and engineers has to be supported to gather an adequate critical mass, sharing manpower, financial resources, knowledge about technology and tools (AIDA WP3).
A strong support for this network is clearly emerging from the AIDA-2 Expressions of Interest
V. Re

3. Microelectronics and 3D integration
The needs of future experiments trigger the interests towards these technologies and their recent progress and evolution. There has to be a strong support for exploiting them in a collaborative way in our community
The microelectronic industry has moved in recent years with a very quick pace pursuing CMOS scaling towards the 10-nm regime.
3D vertical integration of silicon active layers (sensors, analog and digital electronics) has stimulated new ideas for transforming the design of pixel detectors. It still needs to be fully qualified, working together with industry.
V. Re

4. Topics
This talk will cover EoIs dealing with front-end integrated circuits (advanced CMOS, BiCMOS) and their interconnection to silicon pixel sensors (bump bonding, oxide bonding, 3D integration with TSVs).
Some of these EoIs have a larger scope, involving various features of pixel detector systems (sensors, microcooling, light modules,…).
There are obvious links and possible overlaps with the next two talks on infrastructures for pixel sensors and silicon detectors
V. Re

5. Expressions of Interest concerning microelectronics and interconnections
Microelectronics and 3D integration (AIDA WP3 community: Bonn, MPP, MPG Semicon Lab, INFN Genova, Pavia, Perugia, Pisa, Bari, CPPM, IPHC, LAL, LPNHE, Liverpool, Uppsala, AGH, CERN, Barcelona,..)
- demonstrators of advanced 3D integration
- CMOS library in 65 nm and beyond
2) Hybridization of pixel devices (IFAE, Bonn, INFN)
- flip-chip for standard thin pixels and High-Voltage (HV) CMOS sensors
4) Development of pixel modules with reduced inactive edges (MPP, LAL, LPNHE)
- TSV with reduced cross section in 65 nm CMOS chips
14) 3D integration towards large area and cost effective pixel detectors (Bonn)
- Chip-to-wafer, wafer-to-wafer bonding, CMOS sensor on CMOS chip
37) The CLIC detector and physics study (CLIC community)
- Interconnect activities: bump bonding with small pitch, TSV interconnect, capacitive coupling/glue
- Hybrid pixel detector R&D, pushing limits to small pixel sizes, low power, time and amplitude measurement (microelectronic design)
V. Re

6. Why AIDA WP3 groups are interested in a new activity in AIDA-2?
3D integration:
AIDA WP3 successfully tested “low-density” 3D flavors, based on the “via-last” (fully processed CMOS chips) vertical integration of heterogeneous layers (50 – 100 mm density of interconnections and through-silicon vias).
FE-I3 (ATLAS pixel chip), MEDIPIX3, HEXITEC chips with 3D features are available.
This version of 3D technology uses through-silicon vias (TSV) in the chip periphery to reduce dead areas
FE-I3 operated
through TSVs
M. Barbero, T. Fritzsch, L. Gonella, F. Hügging et al., JINST 7 (2012) P08008
There is a strong interest for qualifying more aggressive 3D processes with finer pitch interconnections and TSVs (< 50 mm): this is pushed by the need of smaller pixel cells with complex electronic functions

7. Why AIDA WP3 groups are interested in a new activity in AIDA-2?
65 nm CMOS library, SiGe library, “beyond 65nm” CMOS:
There will be a strong interest in developing 65 nm CMOS readout chips in the coming years, for various applications at LHC phase II upgrades and CLIC (among others)
AIDA WP3 started the work towards the creation of a common library of shared circuit blocks to be used in different chips for various applications to HEP detectors.
Actual common design work is planned in the frame of a contract that is currently been finalized between CERN, IMEC and a CMOS foundry.
In the time frame of AIDA, only a first set of blocks will be submitted and shared. The accomplishment of a full library could be the goal of AIDA-2.
V. Re

8. Deep-submicron microelectronics
CLIC, HL-LHC, etc.
Network of designers, circuit libraries
Stay in pace with technology steps for HEP
130 nm, 65 nm design and beyond
CLICdp => support for this activity to continue
Participation by CLICdp members
Of general interest => many client communities
e.g. RD53
10-bit SAR ADC for Lumical, 130 nm
1.6 mm
64×64
pixels
EoI-1b, EoI-56, EoI-37a
CLICdp institutes interested in participating:
AGH-UST (Marek Idzik)
CERN PH-LCD (Lucie Linssen)
CLICpix demontrator, in 65 nm
Lucie Linssen, CLICdp talk, AIDA-2 meeting, 17/2/2014

9. Advanced interconnect technologies (TSV)
CLIC, HL-LHC, etc.
Advanced TSV interconnect
For low-mass seamless detection modules
CLICdp => support for the interconnect activity to continue in AIDA-2
Participation by CLICdp members
Of general interest => many client communities
TSV project with Medipix3RX, partially funded though AIDA-1
EoI-1a, EoI-56, EoI-37a
CLICdp institutes interested in participating:
CERN PH-LCD (Lucie Linssen)
Lucie Linssen, CLICdp talk, AIDA-2 meeting, 17/2/2014

10. Fine-pitch 3D integration
Pitch of interconnections and TSVs: mm
enable small pitch pixel sensing elements
 improve resolution and reduce pixel occupancy
enable multiple interconnections in a single pixel readout cell of 3D front-end integrated circuit
 Novel readout architectures based on information processing, storage and transmission effectively performed at the level of a pixel or of a region of pixels
Tests with such technologies were already performed by the HEP community, pointing out their very high potential (3D-IC MPW run with Tezzaron/GlobalFoundries).
TSVs
wafer to wafer bonding
V. Re

11. 3D integration demonstrators
An essential task in the new project will have to foresee working together with industry in order to find reliable partners for the full development of 3D integration for HEP detector applications
Several candidates as industrial partners have been suggested in the EoIs
The goal of the network is to build demonstrators where high-density 3D integration is fully implemented, starting with relatively small test vehicles and then possibly fabricating larger-size devices.
Some details about possible AIDA-2 3D demonstrators will be given in the following slides
V. Re

12. TSVs in 65 nm pixel chips
Several groups in the “3D/microelectronics” EoIs propose to use the 65 nm CMOS chips for phase II-upgrade of ATLAS as a test vehicle for 3D integration techniques.
TSVs with reduce cross-section (10 – 30 mm) for backside access.
These chips will be then connected to a high-resistivity, “reduced inactive edge” silicon pixel sensor.
Ultimate goal: four-side buttable detector modules, seamlessly tiled to produce large area detection systems
100 μm
TSVs module
Bonding …
front end chip (65 nm)
back side
front side
P type sensor HV
V. Re

13. HV-CMOS sensors capacitively coupled to a CMOS readout chip
CMOS sensors in high voltage processes with moderate to large depletion zones, bonded through a dielectric layer to the readout chip. Technology for low cost and reproducible capacitor values must be qualified.
FE-I4 (or new 65 nm chip)
capacitive
coupling
using glue
bonding
glue bonding
smart pixels containing amplifier and discriminator for every pixel (~100 transistors) bonded to digital chip (> 100 M transistors) in 65 nm CMOS
HV-CMOS
(I. Peric et al) OR
V. Re

14. HV-CMOS Hybridization
Combine 3 pixels together to fit one FE-I4 pixel (50×250μm2), with HV-CMOS pixels encoded by pulse height.
CCPD: Capacitively coupled to pixel IC.
Active sensor HV-CMOS coupled to FE:
Capacitive coupling through bump pads
Bump-pads are 18µm diameter
Dielectric layerhas to be very thin (<5µm?) and well aligned (< few µm)
Large chips (>2x2 cm2) or W-W bonding
Uniformity of the dielectric layer
Cheap process to be developed
HV-CMOS need signal/power
Engineered solution for module hybridization: TSV?
The tiny HV2FEI4p1 prototype glued on the large FE-I4
FE-I4
HV2FEI4
2.2 × 4.4 mm2.
60 columns × 24rows

15. Via-last integration of 2 layers of 65 nm CMOS circuits
Homogeneous 3D chip with two 65 nm CMOS layers, to be connected to a high-resistivity pixel sensor: first layer with pixel analog readout and ADC, second layer with data processing and storage.
Silicon brokers (MOSIS) are actively polling potentially interested institutions to know how to serve their 3D needs,
Debates are ongoing: 3D in 65nm or 3D in 130nm
in nm process is obsolete, 65nm is becoming cost-wise accessible (vendors differ in costs),
US Universities (NCSU) opened a call for participation in 3D in 65nm (GF process and Tezzaron TSVs) run through MOSIS
Repeating of a 3D run in 130nm process has attractiveness for existing users (Fermilab in touch with MOSIS)
From P. Grybos, AGH-Krakow

16. An interesting option (if available) for 3D 65 nm CMOS readout chips
NEW 3D run: fabrication of TSVs in post-processing 1
Process: almost any bulk CMOS process, considered GF130nm CMOS or GF65nm CMOS
TSVs added in post-processing steps to after wafer bonding (Cu DBI)
Extensive post-processing (thinning, aligned etching of TSVs cavities, metal filling, back-side pad deposition and passivation) = higher costs
Two-side access ICs are possible but with more labor and costs
selected for next 3D-IC run by MOSIS depending upon demonstration of the TSV part by Tezzaron (FERMILAB is processing blank test wafers at Tezzaron now) 3
AIDA, Feb. 17, 2014
From P. Grybos, AGH-Krakow 16

17. Fine-pitch interconnections
The qualification of fine-pitch (50 mm and below) interconnections is an integral part of this activity. The availability of low-mass, high-density bonding processes between small pixel sensing elements and electronic readout cells will be of great interest for future detectors.
Several groups (IFAE, INFN Genova, MPG Semiconductor Lab,…) are interested in qualifying hybridization processes and facilities.
These activities will have to be discussed with the groups interested in infrastructures for pixel sensors.
V. Re

18. Hybridization of Pixel Devices
IFAE infrastructure:
50 m2 clean room (class , 10000, 1000)
Pac-Tech SB2-M Solder Ball Bumper
Suss Microtech FC-150 Flip Chip Bonder
Devoltec 6400 G5 wirebonder
Activity goals:
Flip-chipping techniques for thin devices
Hybridization of prototypes/R&D with solder bumper
Flip-chipping of HV-CMOS modules
Make flip-chipping available for members of the
AIDA-2 interested
Institutions interested:
Bonn, INFN, IFAE (other Spanish/CMS,…)
Cooperation with private sector
Flip-chip
bonder
Wire bonder
Solder ball bumper

19. Fine pitch flip chip bonding
Project proposal
:- exploration of fine-pitch flip chip bonding techniques for future pixel detectors
:- development of Cu pillar FC with different joining method including solder cap, solder bump and Cu-Cu
:- process has to be compatible with state-of-the-art passive and active pixel sensors
:- feasibility study using test vehicles
:- test chips and silicon substrates designed and produced at MPG Semiconductor Lab
:- fine-pitch flip chip studies with industrial FC equipment manufacturer
:- explore limits of these techniques, expect reachable area array pitch around 20 to 30 µm
:- evaluation and reliability studies on assembled test vehicles
Courtesy Unisem
Courtesy ASE
17//2014
Ladislav Andricek, MPG Halbleiterlabor

20. Impact on other fields
It is clear that this program will also enable the HEP community to transfer these microelectronic technologies to other application fields, such as medical imaging and photon science. This will greatly strengthen the role that HEP plays in the European scenario of technological R&D for future particle detectors.
In the current AIDA WP3, very good results for the qualification of 3D processes were achieved with CMOS chip for pixels in photon science
INFN PIXFEL project (L. Ratti et al): pixel detectors at advanced X-ray sources with 65 nm CMOS and 3D integration
Swedish detector platform (R. Brenner):
3D pixel readout chip with a digital tier optimized for non-HEP applications
V. Re

21. CMOS library in 65 nm and beyond
An important goal of a new H2020 project would be to continue the support that was begun by AIDA to a network of microelectronic designers, so that the creation of a full 65 nm CMOS library with analog and digital circuit blocks (the so-called “IP blocks”) is accomplished, with an adequate documentation and maintenance.
This task could be extended to more advanced generations (e.g., 40 nm), that are already available since a few years, but still need to be qualified for their use in future HEP detectors.
SiGe BiCMOS is a very interesting option for applications requiring high speed performance for very high resolution timing and for circuit operation at radio frequencies.
Radiation hardness qualification with the definition of rad-hard design criteria is an integral part of this task.
V. Re

22. C. de La Taille Electronics in particle physics XII ICFA school
SiGe
High speed, low power, large dynamic range process
Best gm/I ratio (40 V-1)
High speed at low current (100 GHz)
Good Early voltage ( V !)
Excellent matching (< mV)
Cryogenic operation (LAr)
Interest for high speed detector readout
Low power PM / SiPM readout
Time and charge measurements (picosecond resolution)
Interest to study several new processes available and share RF design tricks
Tower 180nm, STm 130 nm…
2ns
C. de La Taille Electronics in particle physics XII ICFA school

23. Conclusions
Interests and commitments are wide and strong in the European HEP community for a network on 3D integration and microelectronics in AIDA-2.
Work with industry to qualify high-density interconnections to pixel sensors with < 50 mm pitch and TSVs in 65 nm CMOS chips so that these technologies can be used on a large scale with high yield and reasonable cost
Implement a full 65 nm CMOS library, study other new technologies
A pixel telescope based on 3D integration may be an important goal for AIDA-2 (shared with other working groups), with the implementation of an advanced device that can be used by the community for testing new detectors in high intensity beams.
V. Re

24. Backup slides
V. Re

25. Fast novel vertex/tracker detectors with fast (HV-)CMOS
CLIC, HL-LHC
HV-CMOS MAPS:
180 nm High Voltage process
Vbias ~100 V, μm depletion layer
Integrated sensors, fast signal collection
Hybrid option:
Capacitive Coupled Pixel Detector (CCPD)
HV CMOS chip as integrated sensor+ amplifier
Capacitive coupling to readout chip
through layer of glue => no bump bonding
Ongoing R&D with FEI4, Timepix, CLICpix
EoI-58, EoI-38, EoI-44 , EoI-14, EoI-2, EoI-46, EoI-37
CLICdp institutes interested in participating:
Liverpool (Joost Vossebeld)
Glasgow (Aidan Robson)
Oxford (Phil Burrows)
CERN PH-LCD (Lucie Linssen)
HEP technology advancement !
Towards cheaper vertex/tracking detectors; replacement of expensive bump-bonding
Lucie Linssen, CLICdp talk, AIDA-2 meeting, 17/2/2014