1. Lecture 9 RTL Design Methodology

2. Structure of a Typical Digital System Datapath (Execution Unit) Controller (Control Unit) Data Inputs Data Outputs Control Inputs Control Outputs Control Signals Status Signals

3. Hardware Design with RTL VHDL Pseudocode DatapathController Block diagram Block diagram State diagram or ASM chart VHDL code Interface

4. Steps of the Design Process 1.Text description 2.Interface 3.Pseudocode 4.Block diagram of the Datapath 5.Interface with the division into the Datapath and the Controller 6.ASM chart of the Controller 7.RTL VHDL code of the Datapath, the Controller, and the Top Unit 8.Testbench of the Datapath, the Controller, and the Top Unit 9.Functional simulation and debugging 10.Synthesis and post-synthesis simulation 11.Implementation and timing simulation 12.Experimental testing

5. Steps of the Design Process Practiced in Class Today 1.Text description 2.Interface 3.Pseudocode 4.Block diagram of the Datapath 5.Interface with the division into the Datapath and the Controller 6.ASM chart of the Controller 7.RTL VHDL code of the Datapath, the Controller, and the Top Unit 8.Testbench of the Datapath, the Controller, and the Top Unit 9.Functional simulation and debugging 10.Synthesis and post-synthesis simulation 11.Implementation and timing simulation 12.Experimental testing

6. min_max_average example

7. Circuit Interface n 5 n 2 clk reset in_data in_addr write START DONE out_data out_addr MIN_MAX_AVR

8. Interface Table PortWidthMeaning clk1System clock reset1System reset – clears internal registers in_datanInput data bus in_addr5Address of the internal memory where input data is stored write1Synchronous write control signal START1Starts the computations DONE1Asserted when all results are ready out_datanOutput data bus used to read results out_addr201 – reading minimum 10 – reading maximum 11 – reading average

9. Pseudocode Begin: SUM = SUM + CDATA; if (CDATA < MIN) then MIN = CDATA; endif if (CDATA > MAX) then MAX = CDATA; endif endfor AVR = SUM/32 DONE = 1 goto Begin MAX = 0; MIN = 2 n -1; SUM = 0; for i=0 to 31 do CDATA = M[i]; wait for START;

10. RTL Hardware Design by P. Chu Chapter 1010 Difference between a regular flowchart and ASM chart: –Transition governed by clock –Transition done between ASM blocks Basic rules: –For a given input combination, there is one unique exit path from the current ASM block –The exit path of an ASM block must always lead to a state box. The state box can be the state box of the current ASM block or a state box of another ASM block.

11. RTL Hardware Design by P. Chu Chapter 1011 Incorrect ASM charts:

12. RTL Hardware Design by P. Chu Chapter 1012

13. sorting example

14. Sorting - Required Interface Sort Clock Resetn DataIn N DataOut N Done RAdd L WrInit S (0=initialization 1=computations) Rd

15. Sorting - Required Interface

16. Simulation results for the sort operation (1) Loading memory and starting sorting

17. Simulation results for the sort operation (2) Completing sorting and reading out memory

18. Before sorting During Sorting After sorting Address 01230123 3322111122333322444444431111223433221111223333224444444311112234 i=0i=0i=0i=1i=1i=2 j=1j=2j=3j=2j=3j=3 MiMi MjMj Legend: position of memory indexed by i position of memory indexed by j Sorting - Example

19. Pseudocode wait for s=1 for i=0 to k-2 do A = M i for j=i+1 to k-1 do B = M j if A > B then M i = B M j = A A = M i end if end for Done wait for s=0 go to the beginning

20. Block diagram of the Execution Unit