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MCS51 - lecture 3. Lecture 3 2/30 Timers/counters MCS51.

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Presentation on theme: "MCS51 - lecture 3. Lecture 3 2/30 Timers/counters MCS51."— Presentation transcript:

1 MCS51 - lecture 3

2 Lecture 3 2/30 Timers/counters MCS51

3 MCS51 - timer/counter #0 i #1 3/30 Common features: 16-bit; accessible in SFR as register pairs THx-TLx; counting up; count machine cycles (timer mode) or external pulses (counter mode); external pulses can be gated; controlled by special registers in SFR; overflow (from 0FFFF to 0) sets TFx flag, which can cause interrupt; 3 the same working mode: 0, 1 i 2. Timer/counter #0 can also work in mode 3, then timer/counter #1 is stopped.

4 MCS51 - timer/counter #0 i #1 4/30 GATEC/TM1M0GATEC/TM1M0 TMOD89h Control registers: timer/counter #1timer/counter #0 GATE - set - enables gating of external pulses; C/T - set - counter mode, cleared - timer mode; M1,M0 - select one of working mode: timer/counter #1timer/counter #0 0 0 - mode 00 0 - mode 0(13-bit) 0 1 - mode 10 1 - mode 1(16-bit) 1 0 - mode 21 0 - mode 2(8-bit with reload) 1 1 - disabled1 1 - mode 3(double 8-bit)

5 MCS51 - timer/counter #0 i #1 5/30 TF1 8F TR1 8E TF0 8D TR0 8C IE1 8B IT1 8A IE0 89 IT0 88 TCON88h TF1 - timer/counter #1 overflow flag TR1 - set - starts timer/counter 1 TF0 - timer/counter #0 overflow flag TR0 - set - starts timer/counter 0 8AhTL0 8BhTL1 8ChTH0 8DhTH1 Value registers:

6 MCS51 - timer/counter #0 i #1 6/30 Mode 0 - 13-bit OSC TLx 5bTHx 8b :12 TRx C/T GATE TFx Tx INTx 0101 0101

7 MCS51 - timer/counter #0 i #1 7/30 Mode 1 - 16-bit OSC TLx 8bTHx 8b :12 TRx C/T GATE TFx Tx INTx 0101 0101

8 MCS51 - timer/counter #0 i #1 8/30 Mode 2 - 8-bit with automatic reload OSC TLx 8b THx 8b :12 TRx C/T GATE TFx Tx INTx 0101 0101

9 MCS51 - timer/counter #0 i #1 9/30 Timer/counter #0 mode 3 - double 8-bit OSC TL0 8b TH0 8b :12 TR0 C/T GATE TF0 Tx INT0 0101 0101 TF1 0101 TR1

10 MCS51 - timer/counter #0 i #1 10/30 Counting external pulses (C/T=1): counted falling edges; falling edge on input Tx is detected, if during one machine cycle there is a high level and in the next - low; increment of counter content is done in machine cycle following detected edge; maximal frequency of counted pulses = f CLK :24. machine cycle N-1machine cycle Nmachine cycle N+1 detection of falling edge counter increment 3 / 4 m.c. 1 / 3 m.c.

11 MCS51 - timer/counter #0 i #1 11/30 Possible applications of timer/counter #0 & #1: time interval measure with time-end signalled by interrupt or only TFx flag; clock interrupt; in 8-bit mode with automatic reload on f CLK =12MHz clock interrupt period up to 256  s (3,9kHz); in 16-bit mode with program reload on f CLK =12MHz clock interrupt period up to 65,5ms (15,25Hz); counting external pulses/events.; counting programmed number of pulses and interrupt request; clocking of SIO - only timer #1 !.

12 MCS51 - timer/counter #2 12/30 Features: 16-bit; accessible in SFR as register pair TH2-TL2; counting up; count machine cycles (timer mode) or external pulses (counter mode); 16-bit compare-capture register RCAP2H-RCAP2L; controlled by special registers in SFR; overflow (from 0FFFF to 0) sets TF2 flag, which can cause interrupt; can clock SIO;

13 MCS51 - timer/counter #2 13/30 Control register: TF2 CF EXF2 CE RCLK CD TCLK CC EXEN2 CB TR2 CA C/T2 C9 CP/RL2 C8 T2CON C8h TF2 - timer/counter #2 overflow flag, set by hardware after counter overflow only if bits RCLK i TCLK are cleared EXF2 - falling edge on input T2EX (P1.1) flag, acting only if bit EXEN2 =1 EXEN2 - if set enables detecting of falling edge on T2EX input for example to capture/reload counter TR2 - if set starts timer/counter #2 C/T2 - set - counter mode, cleared - timer mode CP/RL2 - set - capture mode, cleared - reload mode RCLK, TCLK - if set, TF2 flag clocks SIO receiver & transmitter if cleared, timer/counter 1 clocks SIO

14 MCS51 - timer/counter #2 14/30 Work with automatic capture on CP/RL2=1 TCLK=RCLK=0 OSC TL2TH2 :12 TR2 C/T2 EXEN2 TF2 T2 T2EX 0101 0101 RCAP2LRCAP2H EXF2 0101

15 MCS51 - timer/counter #2 15/30 Work with automatic reload on CP/RL2=0 TCLK=RCLK=0 OSC TL2TH2 :12 TR2 C/T2 EXEN2 TF2 T2 T2EX 0101 0101 RCAP2LRCAP2H EXF2 0101

16 MCS51 - timer/counter #2 16/30 Work as SIO clock on RCLK=1 or TCLK=1 OSC TL2TH2 :2 TR2 C/T2 EXEN2 TF1 T2 T2EX 0101 0101 RCAP2LRCAP2H EXF2 0101 :2 :16 RxC TxC SMOD RCLK TCLK 0 1 1 0

17 MCS51 - timer/counter #2 17/30 Possible applications of timer/counter #2: time interval measure with time-end signalled by interrupt or only TF2 flag; clock interrupt; 16-bit reload constant allows to achieve long period of clock interrupt; counting external pulses/events; counting programmed number of external pulses and interrupt request; independent SIO receiver & transmitter clocking; SIO clocking in wide range of frequency; measure of phenomenon duration, which begin and end are signalled by falling edge on T2EX.

18 MCS51 - timer/counter #2 - other modifications 18/30 Work with automatic reload & rectangular waveform output on T2 0101 OSC TL2TH2 :2 TR2 C/T2 EXEN2 optional do SIO T2 T2EX 0101 RCAP2LRCAP2H EXF2 0101 :2 T2OE 0101 f OUT =f OSC /4/(65536-RCAP2)

19 MCS51 - timer/counter #2 - other modifications 19/30 0FFh OSC TL2TH2 :12 TR2 C/T2 TF2 T2 T2EX 0101 0101 RCAP2LRCAP2H EXF2 0101 counting direction: 0 - down; 1 - up counting up: from RCAP2 value up to 0FFFFh counting down: from 0FFFFh down to RCAP2 value Work with automatic reload & switched counting direction (up/down)

20 MCS51 - PCA 20/30 PCA - Programmable Counter Array Features: 16-bit counter accessible in SFR as register pair CH-CL, working as common time base for 5 units; counting up; can counts: divided internal clock pulses or external pulses or timer/counter 0 output pulses; 5 16-bit compare-capture units CCAPxH-CCAPxL; each unit can work in mode: capture, timing, PWM, pulse generation; one unit can work as watch-dog; interrupt request possible;

21 MCS51 - PCA 21/30 Main counter structure - time base IDL CIDL ECF CR CPS0 CPS1 OSC:4 :3 ECI T0OV CLCH CF CCU #0..#4 interrupt system 0101

22 MCS51 - PCA 22/30 Unit in capture mode CCAPnLCCAPnH CCFn interrupt system ECCFn CEXn 0101 0101 CAPPn CAPNn CLCH

23 MCS51 - PCA 23/30 Unit in timing mode CCAPnLCCAPnH CLCH 0101 MATn CCFn interrupt system ECCFn E =? EQ ECOMn write to CCAPnL write to CCAPnH RESET 0 1

24 MCS51 - PCA 24/30 Unit in pulse generation mode CCAPnLCCAPnH CLCH 0101 MATn CCFn interrupt system ECCFn E =? EQ ECOMn write to CCAPnL write to CCAPnH RESET 0 1 0101 TOGn CEXn

25 MCS51 - PCA 25/30 Unit in PWM mode CCAPnL CCAPnH CL OV PWMn CL<CCAPnL E =? CL>CCAPnL ECOMn 0101 CEXn

26 MCS51 - PCA 26/30 Unit #4 as watch-dog CCAP4LCCAP4H CLCH 0101 WDTE RESET E =? EQ ECOM4 write to CCAP4L write to CCAP4H RESET 0 1

27 MCS51 - PCA 27/30 Possible applications of PCA: parallel execution up to 5 task synchronized by common time-base counter; simultaneous, 5-channel measure of phenomenon duration.

28 MCS51 - CCU Philips 28/30 OSC TL2TH2 :12 T2ER T2MS1,T2MS0 T2OV T2 RT2 00 01 11 0 1 CM0 external counter clear T2P1,T2P0 :1/:2 :4/:8 T2BO CML0 CMH0 =? CML1 CMH1 CML2 CMH2 =? CM1 CM2 CTL0CTH0 CT0I CTI0 CTL1CTH1 CT1I CTI1 CTL2CTH2 CT2I CTI2 CTL3CTH3 CT3I CTI3

29 MCS51 - CCU Siemens 29/30 Structure of CCU in 515, 515A of Siemens CCL1+CCH1 CCL2+CCH2 CCL3+CCH3 P1 CRCL+CRCH counter T2 prescaler OSC

30 MCS51 - CCU Siemens 30/30 Timer #2 structure in Siemens MCU with CCU

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