1. 9/28/089/26/2008ECE 561 - Lecture1 Lecture 3 – Common Elements 9/26/20081ECE 561 - Lecture

2. 9/28/089/26/2008ECE 561 - Lecture2 Common Logic Elements Review Lecture 2 sequential elements Examine the data sheet for some of these elements When using element in a design you start with the documentation for the element 9/26/20082ECE 561 - Lecture

3. 9/28/089/26/2008ECE 561 - Lecture3 Common Sequential Elements Basic Element – The Latch – A latch is a level sensitive component that stores and holds a value – What does level sensitive mean? Flip Flops are edge triggered elements – F/F can be constructed of a Master Slave arrangement of 2 latches – Master is level sensitive to new input – On edge master is locked and its value is transmitted to the slave 9/26/20083ECE 561 - Lecture

4. 9/28/089/26/2008ECE 561 - Lecture4 Another Basic Elements Register – Registers are composed of latches or F/Fs – Several uses Register sets – driven from/drive busses Input register for functional units Output hold register for a functional unit Configuration register 9/26/20084ECE 561 - Lecture

5. 9/28/089/26/2008ECE 561 - Lecture5 Edge Triggered F/F Edge triggered flip-flops can be – Master Slave – formed from 2 latches – Discrete design

6. 9/28/089/26/2008ECE 561 - Lecture6 Sequential Components Multiple ICs Cascaded Elements (Registers, Counters) State Machines (FSM) Controllers Cooperating State Machines

7. 9/28/089/26/2008ECE 561 - Lecture7 Data Books Data Books List Components and their parameters

8. 9/28/089/26/2008ECE 561 - Lecture8 More Data Book Components

9. 9/28/089/26/2008ECE 561 - Lecture9 D F/F Data Sheet

10. 9/28/089/26/2008ECE 561 - Lecture10

11. 9/28/089/26/2008ECE 561 - Lecture11

12. 9/28/089/26/2008ECE 561 - Lecture12 The inputs and outputs specs

13. 9/28/089/26/2008ECE 561 - Lecture13 The circuit Implementation

14. 9/28/089/26/2008ECE 561 - Lecture14 Various type of implmentation Note this is A Master-Slave Implementation

15. 9/28/089/26/2008ECE 561 - Lecture15 Timing And has its own Implementation And timing

16. 9/28/089/26/2008ECE 561 - Lecture16 Voltage and Current Specs

17. 9/28/089/26/2008ECE 561 - Lecture17 Higher level components

18. 9/28/089/26/2008ECE 561 - Lecture18 Use of data

19. 9/28/089/26/2008ECE 561 - Lecture19 Use of data You use the data to analyze circuit and then can answer questions on it as illustrated in the following

20. 9/28/089/26/2008ECE 561 - Lecture20 Some Specifications

21. 9/28/089/26/2008ECE 561 - Lecture21 Solution

22. 9/28/089/26/2008ECE 561 - Lecture22 What are the states Develop the state table Pick a state to start with

23. 9/28/089/26/2008ECE 561 - Lecture23 Self Starting Circuits Circuits that end up in a valid state regardless of the state the FSM starts in. Is this circuit self starting? Go to www.wikipedia.com and look at material there on Finite State Machinewww.wikipedia.com