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Published byRosaline Briggs Modified over 9 years ago
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1.4 Hardware Review
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CPU Fetch-decode-execute cycle 1. Fetch 2. Bump PC 3. Decode 4. Determine operand addr (if necessary) 5. Fetch operand from memory (if necessary) 6. Execute 7. Go to step 1 MIPS IA is different from Intel IA Registers PC SP PSW (EFLAGS) What mode are we in? Result of last operation (N,Z,V,C)
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System call = way of obtaining services of OS Often implemented via TRAP instruction
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memory RAM ROM – nonvolatile EEPROM or flash RAM CMOS – low power, volatile RAM Backed up by battery Date/time storage, boot parameters
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Disk organization Disks: sector, intersector gap, track, cylinder
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Multiple programs in RAM Why? Better use of resource, multiple programs running, etc. Needs: Protect processes (and kernel) from each other Handle relocation
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Multiple programs in RAM How? Assume all programs start at virtual address 0 Use base and limit registers Virtual-to-physical address translation via MMU managed by OS Context switch – switching from 1 program to another
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I/O devices Device driver = software that talks to a controller, giving it commands and accepting responses Must be loaded into kernel via one of the following: 1. Relink kernel and reboot (Unix) 2. Make an entry into system file & check & load entries at boot time (Windows) 3. Dynamically loaded drivers (USB & IEEE 1394)
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Methods of communicating w/ device registers: 1.Use special IN/OUT instructions 2.Map device registers into memory (RAM) Methods of performing I/O: 1.Busy waiting 2.Interrupts 3.Interrupts w/ DMA
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Busy waiting User system call driver procedure call wait (polling) return results & status Interrupts User system call driver procedure call w/ ISR specified User waits but CPU is free to do something else ISR is called only when work needs to be accomplished (and performs the work) Interrupts w/ DMA
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Servicing interrupts 1. I/O device has completed operation; CPU is signalled (electrically) 2. CPU may or may not decide to service interrupt right now 3. Service: 1.Push PC & PSW on stack 2.Switch to kernel mode 3.User interrupt vector (table) for service routine address 4.Restore PC & PSW and resume what was being performed Remember: interrupts can occur at any (the worst) time so they can be disabled (ignored, queued, and/or prioritized)
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Buses Standard electrical connectivity w/ system/CPU ( ex. PCI, SCSI, USB, IEEE 1394, IDE, EIDE, ISA, ATA, SATA, AGP, cache, memory) AGP 3.5- 2.1 GB/s ATA- 33 to 133 MB/s FireWire IEEE 1394b- 800 MB/s ISA- 16.7 MB/s (8.3 MHz) PCI- 528 MB/s (66 MHz) SCSI Ultra-640- 640 MB/s USB3- 4 GB/s
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Boot process 1. Execution starts w/ code in BIOS (flash RAM or ROM) 2. Determine amount of memory 3. Scans ISA & PCI for devices and checks keyboard 4. Checks CMOS for boot device First sector of boot device is read into memory and executed
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