1. Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ CprE 281: Digital Logic

2. Transistor Implementation of Logic Gates CprE 281: Digital Logic Iowa State University, Ames, IA Copyright © Alexander Stoytchev

3. Administrative Stuff HW3 is out It is due on Monday Sep 15 @ 4pm. Please write clearly on the first page (in BLOCK CAPITAL letters) the following three things:  Your First and Last Name  Your Student ID Number  Your Lab Section Letter Also, please  Staple your pages  Use Letter-sized sheets

4. Quick Review

5. x 1 x 2 x 1 x 2 + AND gate x x x 1 x 2 x 1 x 2  The Three Basic Logic Gates [ Figure 2.8 from the textbook ] OR gate NOT gate

6. Truth Table for NOT x x xx 0 1 1 0

7. x 1 x 2 x 1 x 2  Truth Table for AND

8. Truth Table for OR x 1 x 2 x 1 x 2 +

9. NAND Gate x1x1 x2x2 f 001 011 101 110

10. NOR Gate x1x1 x2x2 f 001 010 100 110

11. AND vs NAND x1x1 x2x2 f 001 011 101 110 x 1 x 2 x 1 x 2  x1x1 x2x2 f 000 010 100 111 x 1 x 2 x 1 x 2 

12. AND followed by NOT = NAND x1x1 x2x2 f 001 011 101 110 x1x1 x2x2 f 000 010 100 111 x 1 x 2 x 1 x 2  x 1 x 2  f 1 1 1 0 x 1 x 2 x 1 x 2 

13. NAND followed by NOT = AND x1x1 x2x2 f 000 010 100 111 x 1 x 2 x 1 x 2  x1x1 x2x2 f 001 011 101 110 x 1 x 2  f 0 0 0 1 x 1 x 2 x 1 x 2 

14. OR vs NOR x1x1 x2x2 f 000 011 101 111 x1x1 x2x2 f 001 010 100 110 x 1 x 2 x 1 x 2 +

15. OR followed by NOT = NOR x1x1 x2x2 f 001 010 100 110 x1x1 x2x2 f 000 011 101 111 f 1 0 0 0 x 1 x 2 x 1 x 2 +x 1 x 2 +

16. NOR followed by NOT = OR x1x1 x2x2 f 000 011 101 111 x1x1 x2x2 f 001 010 100 110 f 0 1 1 1 x 1 x 2 x 1 x 2 + x 1 x 2 + x 1 x 2 x 1 x 2 +

17. Appendix B Implementation Technology

18. Some Terminology MOSFET - Metal Oxide Semiconductor Field-Effect Transistor NMOS - n-channel MOSFET PMOS - p-channel MOSFET CMOS – complementary MOS (NMOS + PMOS)

19. Figure B.1. Logic values as voltage levels.

20. Figure B.2. NMOS transistor as a switch. DrainSource x = "low"x = "high" (a) A simple switch controlled by the inputx V D V S (b) NMOS transistor Gate (c) Simplified symbol for an NMOS transistor V G Substrate (Body)

21. Figure B.3. PMOS transistor as a switch. Gate x = "high"x = "low" (a) A switch with the opposite behavior of Figure 3.2a V G V D V S (b) PMOS transistor (c) Simplified symbol for a PMOS transistor V DD DrainSource Substrate (Body)

22. (a) NMOS transistor V G V D V S = 0 V V S =V DD V D V G Closed switch whenV G =V DD V D = 0 V Open switch whenV G = 0 V V D Open switch whenV G =V DD V D V Closed switch whenV G = 0 V V D =V DD V (b) PMOS transistor Figure B.4. NMOS and PMOS transistors in logic circuits.

23. (b) Simplified circuit diagram V x V f V DD xf (c) Graphical symbols xf R V x V f R + - (a) Circuit diagram 5 V Figure B.5. A NOT gate built using NMOS technology.

24. Figure B.6. NMOS realization of a NAND gate. V f V DD (a) Circuit (c) Graphical symbols (b) Truth table ff 0 0 1 1 0 1 0 1 1 1 1 0 x 1 x 2 f V x 2 V x 1 x 1 x 2 x 1 x 2

25. Figure B.7. NMOS realization of a NOR gate.

26. Figure B.8. NMOS realization of an AND gate. (a) Circuit (c) Graphical symbols (b) Truth table f f 0 0 1 1 0 1 0 1 0 0 0 1 x 1 x 2 f V f V DD A V x 1 V x 2 x 1 x 2 x 1 x 2 V

27. Figure B.9. NMOS realization of an OR gate.

28. Figure B.10. Structure of an NMOS circuit.

29. Figure B.11. Structure of a CMOS circuit.

30. Figure B.12. CMOS realization of a NOT gate. (a) Circuit V f V DD V x (b) Truth table and transistor states on off on 1 0 0 1 fx T 1 T 2 T 1 T 2

31. Figure B.13. CMOS realization of a NAND gate.

32. Figure B.14. CMOS realization of a NOR gate.

33. Figure B.15. CMOS realization of an AND gate.

35. NAND and NOR gates with n inputs [ Figure 2.25 from the textbook ]

36. Figure B.57. High fan-in NMOS NAND gate.

37. Figure B.58. High fan-in NMOS NOR gate. x k V f V DD V x 1 V x 2 V

38. Questions?

39. THE END