1. Novel Metal-Oxide-Semiconductor Device
學生 : 黃仕澔
指導教授 : 劉致為 博士

2. Strained Si/SiGe Heterojunction Tri-gate FETs
Electrical Characteristics of High-k Material
High-k Reliability

3. Strained Si/SiGe Heterojunction Tri-gate FETs

4. INTRODUCTION DEVICE STRUCTURE NMOS DEVICES PMOS DEVICES SUMMARY
OUTLINE
INTRODUCTION
DEVICE STRUCTURE
NMOS DEVICES
PMOS DEVICES
SUMMARY

5. By incorporating the strained Si channels
INTRODUCTION
By incorporating the strained Si channels
⇨ enhance the carrier mobility
⇨ Strained Si/SiGe heterojunction to control the channel position
NMOS:
(1) Enhanced current drive
(2) Improved subthreshold swing
PMOS:
Very limited enhancement of current drive

6. DEVICE STRUCTURE The strained Si/SiGe FinFET structure.
(a) 3D schematic diagram (The spacers between source/drain and gate are not shown in order to reveal the fin structure)
(b) Cross-section view along A-A’

7. DEVICE STRUCTURE 3D Simulation :
A fully strained Si and a fully relaxed SiGe are used in simulation
assumption:(1) strained-Si is thin enough (2) strained Si/ relaxed SiGe is in the metastable state due to the low thermal budget
- Structure Details
(1) channel doping of 1016cm-3
(2) dual polysilicon gate (n+ for NMOS, p+ for PMOS)
(3) 1.5 nm gate oxide
(4) abrupt source/drain-to-channel junctions
(5) and a Si0.8Ge0.2 body with fixed 5 nm surrounding Si
- Physics Model
(1)The mobility enhancement factors
- In starined Si: electron:1.7x hole:2x
- In SiGe body: electron : 0.25x hole: 0.6x
(2) Drift-Diffusion Model
(3) Heterojunction band alignment

8. NMOS DEVICES
Electron distribution along the A-A’ cross-section under 3 bias conditions for
(a) control device
(b) strained Si/ SiGe NMOS
Bias conditions:
subthreshold region:
VGS-VT = -0.1V
@ threshold:
VGS-VT= 0V
> threshold region:
VGS-VT = 0.3V.

9. NMOS DEVICES Dependence of subthreshold swing on fin width T
A narrower fin width shows lower subthreshold swing
The subthreshold swing is improved in the strained Si/SiGe device as compared to the control device

10. NMOS DEVICES Dependence of subthreshold swing on channel length Lg
A shorter channel length shows higher subthreshold swing
The subthreshold swing is improved in the strained Si/SiGe device as compared to the control device

11. Strained Si/SiGe device has a slightly smaller roll-off
NMOS DEVICES
Threshold voltage roll-off characteristics.
Strained Si/SiGe device has a slightly smaller roll-off

12. Larger LD has larger barrier lowering ⇨yields a more negative VT
NMOS DEVICES
LD dependence on DIBL
Larger LD has larger barrier lowering
⇨yields a more negative VT
H is the fin height
G. Pei et al., IEEE Trans. Electron Device, 2002.

13. PMOS DEVICES
Hole distribution along the A-A’ cross-section under three different bias conditions for
control device
strained Si/SiGe PMOS
Bias conditions:
subthreshold region :
VGS-VT = 0.1V
@ threshold region:
VGS-VT = 0 V
> threshold region:
VGS-VT = -0.3V.

14. PMOS DEVICES
The band diagram of the strained Si/SiGe device and control device
Due to band offset at Si/SiGe heterojunction
⇨ the hole inversion layer can be formed at less negative gate voltage

15. PMOS DEVICES Dependence of subthreshold swing on fin width T
A narrower fin width shows lower subthreshold swing
The strained Si/SiGe device shows higher subthreshold swing than the control device.

16. PMOS DEVICES Dependence of subthreshold swing on channel length Lg
A shorter channel length shows higher subthreshold swing
The the strained Si/SiGe device shows higher subthreshold swing than the control device

17. Strained Si/SiGe device has a slightly larger roll-off
PMOS DEVICES
Threshold voltage roll-off characteristics.
Strained Si/SiGe device has a slightly larger roll-off

18. SUMMARY
This novel strained Si/SiGe FinFET with the enhanced carrier mobility and heterojunction confinement is demonstrated with greatly improved performance for NMOS by 3-D simulation
The PMOS is not improved as much as NMOS due to the buried channel at the Si/SiGe heterojunction

19. Electrical Characteristics of High-k Material

20. OUTLINE
INTRODUCTION
DEVICE STRUCTURE
RESULTS
SUMMARY

21. MOSFET Structure INTRODUCTION Gate oxide+ L
Gate oxide
• Speed Increases with Charge Carrying Capacity, Q = CV.
C=ε/ t
εinsulator : 3.9~40
ε= εinsulator ․ ε0
t : Insulator thickness (<5nm)

22. DEVICE STRUCTURE
Device structure before and after oxidation

23. Hf(0.5nm)/RTO oxide(1nm)
4000C RTO
(N2+O2(0.5%),30s)
6000C
(N2,30s)
8000C
5000C RTO
6000C RTO
Cet(nm):1.7
Cet(nm): 1.6
Cet(nm): 1.3
Cet(nm): 1.4
bad
good
*good --- the CV-curve is better. Because I get the low frequency CV-curve.
Cet(nm): 1.9

24. HfN(0.5nm)/RTO oxide(1nm)
4000C RTO
(N2+O2(0.5%),30s)
6000C
(N2,30s)
8000C
5000C RTO
6000C RTO
Cet(nm): 1.4
Cet(nm): 1.8
Cet(nm): 2.1
Cet(nm): 2.6
1.9(at -1.8v)
Cet(nm): 2.2
bad
good
*good --- the CV-curve is better. Because I get the low frequency CV-curve.

25. The Jg-Vg of Hf and HfN oxidation.

26. SUMMARY
The C-V curve with RTO at 600oC and PDA at 800oC measured at the lowest frequency (50Hz) could be got, and its C-V in accumulation region is the flattest compared with other samples.

27. High-k Reliability

28. OUTLINE
INTRODUCTION
DEVICE STRUCTURE
EXPERIMENT and RESULTS
SUMMARY

29. INTRODUCTION ultra thin oxide, tunneling current
negative bias at gate electrode (accumulation)
electron tunneling
hole + e- => h

30. DEVICE STRUCTURE
Cross-section TEM micrograph of HfO2 on p-type Si wafer, after 300 sec post deposition annealing at 600 ℃.

31. EXPERIMENT and RESULTS
Time evolutions of light emission intensity for (a)H2- and (b)D2-treated devices under constant current stress at 100 mA.

32. EXPERIMENT and RESULTS
Recoverable Jg -Vg curves incorporating H2 treatment with constant current stress at 100 mA for 104 sec.

33. EXPERIMENT and RESULTS
Recoverable Jg -Vg curves incorporating D2 treatment with constant current stress at 100 mA for 104 sec.

34. SUMMARY
Deuterium -treated technology provides slightly better reliability improvement on optical reliability