1. Low Power Processor Design VLSI Systems Lab. 3 월 28 일 박 봉 일

2. Introduction Processor power consumption Power 1 Watt 3-5 Watt 5-15 Watt 15+ Watt heat sink, air flow fan sink exotic none $1-5 $10-15 $50+ CostStrategy Laptop Computer Low power processor

3. Power Reduction Technique Process level –low voltage –low capacitance Circuit level –TR sizing –adiabatic circuit –low power arithmetic components Logic level –precomputation logic –logic synthesis –retiming System level –frequency reduction –voltage reduction –power management mode

4. System Level Execution unit idle time(PowerPC 603)

5. System Level Power management support

6. Power Estimation Simulation-based techniques –circuit simulation –switch level simulation : IRSIM –transistor level simulation : PowerMill –gate level simulation –Monte Carlo simulation

7. Power Estimation Probabilistic techniques –combinational circuits zero delay model real delay model –sequential circuits

8. Logic Level Logic Synthesis –precomputation logic –retiming –state assignment –path balancing –technology mapping –gate resizing g R R R1 R2 A R3 g

9. Memory Architectural selection –select as little of the array as possible –dynamically powering up sense amp. –Clocking only as needed 1/2 Cell Array 1/2 Cell Array Row De- coder 1/2 Column Decoder 1/2 Column Decoder Split Array, half of columns active W/R Data Addr Memory Block Diagram

10. Clock Fast transition time and low skew –consume lots of power –10~20% of total chip power Clock power management –clock branches are segmented and can be enabled as needed PLL

11. Datapath Signal Activity PowerPC 601 Instruction Type# of instructions# of 0 to 1# of 1 to 0 Shift31751.984.63 Switching Factor 0.21 ADD/SUB49373.414.310.24 EA calculation154963.152.370.17 MUL/DIV10701.501.560.10 Control Register1921.442.260.12 Compare23493.814.110.25 Branch585.0313.500.58 Total272773.053.130.19

12. Traditional Method Use enabling logic –Enable only the adder needed –reduce the signal activities Minimizing temporal bit transition activity –gray coding –bus inversion coding Adder MUX clk control clk control clk control clk control ABCD ABCD

13. Datapath Components: Adder 특징 – 다양한 구조에 따른 transition 의 변화가 심함 Adder Type (32 bit) Delay (in gate units) # of gates # of transitions (average) Ripple Carry68288182 Carry Skip(1)33304392 Carry Skip(2)19350437 Carry Lookahead14401405 Carry Select14597711 Conditional Sum158571323

14. Datapath Components: Multiplier 특징 – 많은 transition –transition 이 일어날 확률이 1 회 /1clock 인 노드가 50% 이상임 Multiplier Type (32 bit) Delay (in gate units) # of gates # of transitions (average) Modified Array9824057348 Wallace/Dadda5125693874

15. Future Works 저전력 프로세서 설계 –Arithmetic component 에 대한 분석 – 저전력을 위한 arithmetic component 의 제안 저전력 프로세서 구조의 제안 – 다양한 구조에 대한 전력측면에서의 분석

16. Continued Story: ACCENT_Light VLSI Systems Lab. KAIST. Mar. 28. 1998. You-Sung Chang

17. Previous Work Dr. Bong has done! Everyone knows well now. Nothing to explain.

18. Feature of Accent Highly integrated CISC Processor-Core 4-stage Pipelined Architecture Configuration –Pre-fetch Cache –Decode –Execution –Memory Management –Micro-code –External Interface –Embedded DRAM –...

19. Low Power in Accent Support Programmable Very Complex Code Micro-code based Stripe Power Control Pre-charging Biasing in Mask-ROM Inverse Data Store in Embedded DRAM Minimizing switching in BUS transfer

20. Very Complex Code Maximize the advantage of CISC micro-code approach Adaptive Programmable Micro-code –Program analyzer extract application specific instruction –Compile micro-code ROM and decoder A small loop is translated into a complex instruction –Small code size –Give more idle time to pre-fetch and decode units –Enable low power from the small code size and the clock blocking for the induced idle time of pre-fetch and decode units

21. Stripe Power Control Clocking only as needed –Obvious! –How? Cut data-path in strips Power control using micro-code field information Request enables clocking for peripheral units Func1 F/F Pass Latch Gated clock 1 Gated clock 2 Func2 F/F Pass Latch Gated clock 3 Gated clock 4

22. Mask ROM Selective pre-charging/discharging for Micro-code ROM. Using the static statistics, assemble Micro-code ROM cell column by column. Simulation shows –Not so effective for Micro-code ROM –Some potential for constant ROM

23. Embedded DRAM Full voltage pre-charging –Does not need half voltage generator Single-ended type Read/Write word by word To save power, minimize switching in the bit-line Store inverse data if ‘0’ is dominated with indicator. Sense Amplifier Reference Pre-charged (low cap.) Pre-charged (high cap.)

24. BUS Transfer One-Hot Coding Gray Coding Bus Inversion Coding(1994 stan) BUS N+1 1: inversion indicator NN

25. Self Evaluation Evaluation of Anticipation –Support Programmable Very Complex Code(H) –Micro-code based Stripe Power Control(M) –Pre-charging Biasing in Mask-ROM(M) –Inverse Data Store in Embedded DRAM(H) –Minimizing switching in BUS transfer(X) H: high M: medium L: low X: X, its dedicated signification

26. Further Work Complete power estimation for each block –Functional Blocks in Data-path –Pre-fetch and Decoder Inspect physical constraints in pre-charging biasing Estimate the power advantage of inverse data store Target : Workshop ~ Task force : Caviar, Woosee, Bipark