1. AMS HVCMOS status Raimon Casanova Mohr 14/05/2015

2. Let’s put HVCMOS AMS designs and concepts in order HVCMOS desings are in fact: – High Voltage (HV) – High Resistivity (HV) High resistivity depends of the foundry: – H18 technology has been "installed" at AMS - the chips were so far produced by IBM – AMS is ready to adapt the processes – it is possible to implement the HV 180nm and 350nm (H18/35) processes on high resistive wafers – wafers of 20 (standard), 80, 200 Ohm cm and 1kOhm cm.

3. Let’s put HVCMOS AMS designs and concepts in order The final goal of the collaboration is to create a monolithic detector: – Hybrid solution: RD53 + sensors -> inner layers – Monolithic solution: external layers Several groups working on different technologies: – Bonn + SLAC: Lfoundry – CPPM: Global Foundries

4. Let’s put HVCMOS AMS designs and concepts in order CCPD H18 developments: – status (CCPDv2 and v4): The efficiency before irradiation is >99% after irradiation ~95%. This is all on low resistive wafers – The only problem is the reduced time resolution (~100ns) which is the result of time walk. Cause – weak signals – An improved version of the detector CCPDv5 has been submitted in February and will available ~ June. This chip has improved guard ring structure (already tested on H35 prototypes) which allows twice as higher bias voltage (120V instead 60V) – Additionally, a novel circuit for time walk compensation has been implemented. If everything is according to simulations, this chip will have the required timing and efficiency although on low resistive substrates. – If this design is implemented on a high resistive material we will have an increase of signal and decrease of detector capacitance/noise. If signals increase time walk is less.

5. Let’s put HVCMOS AMS designs and concepts in order CCPD H35 developments: – the H35 CCPDv1 (the first ATLAS test chip in 350nm AMS submitted last year in August) is under test - the chip works. – the guard ring structure has been changed and use 120V bias voltage (before was possible 60V). – the chip with x-rays has been radiated at KIT (6MRad - the most critical dose, after it gets better) it works. – the H35 CCPDv2 with the time walk compensated comparator (submitted in February) will be tested soon.

6. Let’s put HVCMOS AMS designs and concepts in order Mu3e: – Mu3e chip for the Mu3e experiment – The concept is that the pixels are simple (only amplifier) they sent the analog signals to the periphery. – Every pixel has one dedicated periphery cell. The periphery cells work in the same way as the digital pixel parts of FEI3. After a hit, time stamp is stored. Hit data are sent to EOC via buses. Mu3e chip does not support trigger, all data as sent via GBit link out of the chip. – The present Mu3e chip is in principle radiation tolerant since its analog part is based on the CCPDv1 design. – It is probably easy to make the chip fully rad hard, just several transistors should be enclosed.

7. AMS HV-CMOS: Status and Plans We are currently working on the following designs – 50um x 250um active pixels readout by FEI4 (CCPD or bump bonded) – 50um x 250um active pixels connected to on-chip readout block (monolithic pixels) – 33um x 125um active “smart” pixels readout by FEI4 (CCPD or bump bonded) – 40um x 800um pixels (segmented strips) connected to on-chip readout block (monolithic pixels with external digital chip that does triggering) (coordinated by Santa Cruz) – 25um x 25um active pixels readout by CLICPIX (CCPD) Several engineering runs are planned in AMS H35 HVCMOS technology and in AMS H18 HVCMOS technology Engineering run 1 in H35: – The chip will be about 1.9cm x 2.5cm large – It will contain several pixel matrices: 1)one pixel matrix of 1.5cm(?) x 1.2cm size that can be segmented into 6 pixel flavors if needed (pixel type 1 – CCPD/Bump) 2) Two pixel matrices 1.0 x 0.4 cm size (pixel type 2 – CCPD/monolithic) 3)Two additional matrices with test structures (e.g. smart pixels) (each 0.5 x 0.4 cm size) – The wafer resistivities will be ~80, ~200 and ~ 1000 Ohm cm (maybe also 20 Ohm cm) Engineering run 2 in H35 – strip project (coordinated by Santa Cruz) Engineering run 3 in H18 (~October) (high resistivities) – The run will be shared between ATLAS, Mu3e and CLIC – Contains small pixels 3 and 5, as well as monolithic pixels Engineering run 4 in H35 (large pixels)

8. Summary of Ivan visit to AMS Meeting with AMS in their fab on 29th April AMS is very interested for the projects at CERN AMS is ready to adapt the processes – it is possible to implement the HV 180nm and 350nm (H18/35) processes on high resistive wafers Chosen wafers: 20 (standard), 80, 200 Ohm cm and 1kOhm cm H18 technology has been "installed" at AMS - the chips were so far produced by IBM The design rules and the transistor parameters of the "Austrian" H18 process are the same as for IBM, except for the last metal layer. The rules are in this case more relaxed. The new process uses only aluminum (no copper as in IBM) A small test chip will be submitted for the internal run that starts next week It will submit then the "demonstrator" as an engineering run in AMS H18 (180nm) in November (hi res wafers).

9. Back up slide