1. WP1 WP2 WP3 WP4 WP5 COORDINATOR WORK PACKAGE LDR RESEARCHER ACEOLE MID TERM REVIEW CERN 3 RD AUGUST 2010 Work Package 2 Radiation-hard ASIC building blocks for detector data readout systems José Pedro Cardoso

2. WP1 WP2 WP3 WP4 WP5 COORDINATOR WORK PACKAGE LDR RESEARCHER ACEOLE MID TERM REVIEW CERN 3 RD AUGUST 2010 Name: José Pedro Cardoso Nationality: Portuguese Age: 37 Education : MSc. in Electrical and Computer Engineering BSc. In Electronics and Telecommunications Engineering Joined ACEOLE’s Program: 1 st of June 2009 Personal Data 2

3. WP1 WP2 WP3 WP4 WP5 COORDINATOR WORK PACKAGE LDR RESEARCHER ACEOLE MID TERM REVIEW CERN 3 RD AUGUST 2010 Context CERN field of Research How the project fits into the bigger picture Training/Education: Secondment Workshops and conferences Technical training Complementary training Project: Research goal and achievements Milestones Dissemination: Targeted conferences Timeline Next two years Impact and Future work CERN Career Overview 3

4. WP1 WP2 WP3 WP4 WP5 COORDINATOR WORK PACKAGE LDR RESEARCHER ACEOLE MID TERM REVIEW CERN 3 RD AUGUST 2010 Context Training and Education Project Dissemination Timeline 4 Impact and future Work

5. WP1 WP2 WP3 WP4 WP5 COORDINATOR WORK PACKAGE LDR RESEARCHER ACEOLE MID TERM REVIEW CERN 3 RD AUGUST 2010 Context Source:[1] 5

6. WP1 WP2 WP3 WP4 WP5 COORDINATOR WORK PACKAGE LDR RESEARCHER ACEOLE MID TERM REVIEW CERN 3 RD AUGUST 2010 Context Project Training and Education Dissemination Timeline 6 Impact and future Work

7. WP1 WP2 WP3 WP4 WP5 COORDINATOR WORK PACKAGE LDR RESEARCHER ACEOLE MID TERM REVIEW CERN 3 RD AUGUST 2010 On- job Training Phase Locked Loops Noise theory IC Design Tools – Cadence (Mixed Signal) Software tools- MatLab and Mathematica Presentation “Design of High Performance Oscillators” Courses “PLL’s, VCO’s and Frequency Synthesizers (June 2009)” “Nanoscale CMOS analog design from devices to system” (September 2009) “Leaders in Science” (June 2010) Training 7

8. WP1 WP2 WP3 WP4 WP5 COORDINATOR WORK PACKAGE LDR RESEARCHER ACEOLE MID TERM REVIEW CERN 3 RD AUGUST 2010 Title: Design of Low-Noise and Radiation Tolerant Readout Systems 1 st semester (2009/2010) Microelectronic and Micro-Electro-Mechanical Technologies Test and Design for Testability Digital Communication Systems Seminars Projects: Design of a low-phase noise VCXO running at 80 MHz Design of a jitter measurement circuit, based on a new Vernier Delay Line MEM’s Based Oscillator Education - PhD in Electrical and Computer Engineering 8

9. WP1 WP2 WP3 WP4 WP5 COORDINATOR WORK PACKAGE LDR RESEARCHER ACEOLE MID TERM REVIEW CERN 3 RD AUGUST 2010 Context Project Training and Education Dissemination Timeline 9 Impact and future Work

10. WP1 WP2 WP3 WP4 WP5 COORDINATOR WORK PACKAGE LDR RESEARCHER ACEOLE MID TERM REVIEW CERN 3 RD AUGUST 2010 Circuit is divided as follows: PLL Test and Control PLL features: Lock Detection Automatic Oscillation Amplitude Control Built-in Self Test is divided as follows: Calibration Frequency Offset Measurement Jitter Measurement Control block: acts as the referee block, allowing external commands Fuse bank: stores default values Project 10

11. WP1 WP2 WP3 WP4 WP5 COORDINATOR WORK PACKAGE LDR RESEARCHER ACEOLE MID TERM REVIEW CERN 3 RD AUGUST 2010 Phase Locked Loop (PLL) Measures phase difference of two signals Comprises, mainly, the following blocks: Phase Detector, Loop Filter, Voltage-Controlled Oscillator Frequency Divider – dividing factor of 2 PLL Operation Modes 11 Stand-alone operation The circuit should be low noise and insensitive to Process-Voltage- Temperature (PVT). The central frequency is generated applying a voltage to the VCXO

12. WP1 WP2 WP3 WP4 WP5 COORDINATOR WORK PACKAGE LDR RESEARCHER ACEOLE MID TERM REVIEW CERN 3 RD AUGUST 2010 Crystal frequency = 80.1572 MHz Nominal output frequency - 80 MHZ Locking range = 40.0786 MHz ± 8 kHz Output Jitter < 7 ps 130 nm CMOS Technology One frequency multiplication mode: × 2 Power supply voltage: 1.5 V PLL specifications 12

13. WP1 WP2 WP3 WP4 WP5 COORDINATOR WORK PACKAGE LDR RESEARCHER ACEOLE MID TERM REVIEW CERN 3 RD AUGUST 2010 Component-Invariant VDL [2] This on-chip circuit is able to measure Jitter up to 15 ps Jitter is measured counting the number o pulses at logical level “1” Advantages: avoids a large waist of silicon area since only one counter is used all the delays on a VDL are replaced by a single delay in each path Challenges Requires a very good reference Resolution depends on timing difference between oscillators Jitter Measurement Circuit Source:[2] 13

14. WP1 WP2 WP3 WP4 WP5 COORDINATOR WORK PACKAGE LDR RESEARCHER ACEOLE MID TERM REVIEW CERN 3 RD AUGUST 2010 Context Training and Education Dissemination Project Timeline 14 Impact and future Work

15. WP1 WP2 WP3 WP4 WP5 COORDINATOR WORK PACKAGE LDR RESEARCHER ACEOLE MID TERM REVIEW CERN 3 RD AUGUST 2010 Targeted conferences: (Event / Call for Papers) PRIME 2011 – July 2011 / February 2011 TWEPP 2011 – September 2011 / May 2011 DCIS 2011 – November 2011 / March 2011 IMS3TW 2011– June 2011 / February 2011 ITC 2011– October 2011 / June 2011 DATE 2012– March 2012 / September 2011 Dissemination 15

16. WP1 WP2 WP3 WP4 WP5 COORDINATOR WORK PACKAGE LDR RESEARCHER ACEOLE MID TERM REVIEW CERN 3 RD AUGUST 2010 Context Training and Education Dissemination Project Timeline 16 Impact and future Work

17. WP1 WP2 WP3 WP4 WP5 COORDINATOR WORK PACKAGE LDR RESEARCHER ACEOLE MID TERM REVIEW CERN 3 RD AUGUST 2010 May 2010 - January 2011 Design of a Phase Locked Loop with Built-In Self test capabilities. The design should focus on a very low phase-noise circuit. Tape-out of the circuit Feb 2011 - Mar 2011 Design and setup of the test session (pcb design, tester software, radiation lab setup) Test of the circuit Apr 2011 - Jul 2011 Doctoral Programme Second Semester. Submit articles to target conferences Sep 2011 - Jun 2012 Development of a 10 GHz VCO Participation in targeted conferences Jun 2012 - Sep 2012 Dissertation’s writing. Timeline 17

18. WP1 WP2 WP3 WP4 WP5 COORDINATOR WORK PACKAGE LDR RESEARCHER ACEOLE MID TERM REVIEW CERN 3 RD AUGUST 2010 Context Training and Education Dissemination Project Timeline Impact and future Work 18

19. WP1 WP2 WP3 WP4 WP5 COORDINATOR WORK PACKAGE LDR RESEARCHER ACEOLE MID TERM REVIEW CERN 3 RD AUGUST 2010 On the Project – Design of a very low-phase noise PLL/oscillator with Built-In Self Test capabilities. On testing time and cost – can be reduced as test circuitry is implemented on-chip On work’s methodology – a top-down analysis, with the development of macro simulation algorithms, provides an improved integrated circuits’ design method. On my career – Interaction with experts at CERN, FEUP (associated partner) and conferences, has increased my knowledge as well as my skills while a designer. On my education – I had the opportunity to engage on a Doctoral Programme in which the research subject was agreed between FEUP and CERN. Impact 19

20. WP1 WP2 WP3 WP4 WP5 COORDINATOR WORK PACKAGE LDR RESEARCHER ACEOLE MID TERM REVIEW CERN 3 RD AUGUST 2010 Blocks to be designed Calibration PLL mode - the auto calibration feature allows centring of the VCXO tuning range relating to the reference clock frequency. Oscillator mode - the auto calibration logic can be used to quickly choose the VCXO parameters that have to be programmed in the Fuse-Bank to tune the oscillation frequency. Frequency Offset Measurement Measures the offset between the central frequency and a reference Fuse Bank Fuses the default configuration of the PLL, after calibration. Uses a dynamic memory to operate in modes demanded by the user Control Interface Controls all the circuit operation and interfaces with the user with a 8-bit bus. AOAC The amount of power must be chosen in order to decrease phase-noise, and not to stimulate other crystal’s resonant modes, rather than the sheering of the crystal. Future Work 20

21. WP1 WP2 WP3 WP4 WP5 COORDINATOR WORK PACKAGE LDR RESEARCHER ACEOLE MID TERM REVIEW CERN 3 RD AUGUST 2010 [1] - https://espace.cern.ch/GBT-Project/default.aspxhttps://espace.cern.ch/GBT-Project/default.aspx [2] - Chan, A. & Roberts, G. (2002), 'A deep sub-micron timing measurement circuit using a single-stage Vernier delay line''Custom integrated circuits conference', 77--80. [3] - https://espace.cern.ch/proj-gbt10/default.aspxhttps://espace.cern.ch/proj-gbt10/default.aspx References 21 [4] - Allen, P.; Holberg, D.; Allen, P. & Allen, P. (2002), CMOS analog circuit design, Oxford University Press New York. [5] - Gardner F.M. (2005), Phaselock techniques,Wiley-Blackwell [6] - Best R.E., Phase-locked loops, McGraw-Hill Professional Bibliography

22. WP1 WP2 WP3 WP4 WP5 COORDINATOR WORK PACKAGE LDR RESEARCHER ACEOLE MID TERM REVIEW CERN 3 RD AUGUST 2010 Thank you for your attention 22