1. SiNANO Workshop, Montreux, Sept 2006 New Generation of Virtual Substrates T. Grasby Dept. of Physics, University of Warwick

2. SiNANO Workshop, Montreux, Sept 2006 Straining Silicon with a Virtual Substrate Si template (i.e. wafer) New template (virtual substrate) Si wafer strained silicon (biaxial tensile) Device Layer SiGe x(z) unstrained silicon z

3. SiNANO Workshop, Montreux, Sept 2006 Why Global Strain? Non, Non Uniaxial process-induced strain more effective, more flexible Riddled with defects Expensive to produce

4. SiNANO Workshop, Montreux, Sept 2006 Why Global Strain? GLOBAL STRAIN FOR EVER Enables high (biaxial) stress levels ~ 0.9 GPa per 10% Ge concentration (y) Comparably high uniaxial strain via patterning Hybrid strain regime – global + process induced top-up Platform for n-sSi/p-SiGe dual channel CMOS devices Contender for 32-22nm node FDSOI Needed for R&D on strained Ge devices Route to Si-Ge-GaAs integration?

5. SiNANO Workshop, Montreux, Sept 2006 Big Questions  is the quality there?  is there a route to production?

6. SiNANO Workshop, Montreux, Sept 2006 First Generation VS (linear Ge grade) – Quality Issues Ge conc(y) ~ 20% - good for nMOS performance → threading (field) dislocation density (TDD) ≥ 10 5 cm -2 → pile-up densities (PUD) ~ 0.1 – 10 cm -1 → surface roughness ~ 1 – 3 nm  involve CMP

7. SiNANO Workshop, Montreux, Sept 2006 Linear Grading – State of the Art From Y. Bogumilowicz et al., LETI and IQE TDD (cm -2 ) RMS roughness (nm) Germanium composition (%) Pile-up TDD Field TDD RMS

8. SiNANO Workshop, Montreux, Sept 2006 Linear Grading – State of the Art From Y. Bogumilowicz et al., LETI and IQE TDD (cm -2 ) RMS roughness (nm) Germanium composition (%) Pile-up TDD Field TDD RMS

9. SiNANO Workshop, Montreux, Sept 2006 Terrace Grading Thickness (  m) 246 8 10% 20% 0 Ge Concentration Linear grade

10. SiNANO Workshop, Montreux, Sept 2006 UK SiGe:C Epitaxy Centre MBE - V90S-ANT LP-CVD - ASM Epsilon 2000E...from Lab to Fab SS-MBE GS-MBE/-CVD mode

11. SiNANO Workshop, Montreux, Sept 2006 Terrace Grading – development work (SS-MBE) 30% - 3 tier

12. SiNANO Workshop, Montreux, Sept 2006 Terrace Graded - TEM 60% 6 Tier

13. SiNANO Workshop, Montreux, Sept 2006 ≈10 5 cm -2 TDD Pile-up ≈1 cm -1 LG 30%

14. SiNANO Workshop, Montreux, Sept 2006 Defect reveal in 10 4 cm -2 range TDD ≈ 4 x 10 4 cm -2

15. SiNANO Workshop, Montreux, Sept 2006 Defect Reveal in 10 3 cm -2 range LG 15%, 850ºC Pseudo Pile-up EPD = 6x10 3

16. SiNANO Workshop, Montreux, Sept 2006 Hardly an etch pit in sight! Pile-up < 0.1cm -1 TDD ≈ 3x10 3 cm -2 PUD = 0 TD

17. SiNANO Workshop, Montreux, Sept 2006 Pile-up ≈ 5cm -1 LG 40% TDD ≈ 10 6 cm -2

18. SiNANO Workshop, Montreux, Sept 2006 TDD ≈ 3x10 5 cm -2 Pile- up = 0? TG 40%

19. SiNANO Workshop, Montreux, Sept 2006 Terrace Grading – Elimination of Pile-ups? SiPHER Analysis TG (3 tier) up to 30% (SS-MBE) Measurements taken by Accent Optical Technologies near wafer centres Photoluminescence image Surface image 6x6 mm area Pile-up density: ≤ 0.1 cm -1

20. SiNANO Workshop, Montreux, Sept 2006 Terrace Grading – Elimination of Pile-ups? SiPHER Analysis 6x6 mm area Pile-up density: ≤ 0.1 cm -1 3 tier up to 30% (SS-MBE) Measurements taken by Accent Optical Technologies near wafer centres Photoluminescence image Surface image 2x2 mm area Pile-up density: 3.5 - 6 cm -1 Photoluminescence image LG TG

21. SiNANO Workshop, Montreux, Sept 2006 How does Terrace Grading do it? LG

22. SiNANO Workshop, Montreux, Sept 2006 What can Terrace Grading do? LG TG Terrace Grading ≡ Virtual CMP

23. SiNANO Workshop, Montreux, Sept 2006 30% Terrace Graded Properties (MBE growth) High T growth (850  790C) y = 0.3 LG High T TG High T TDD (cm -2 ) PUD (cm -1 ) ~ 1.00 RMS roughness (nms) (20x20μm) ~ 53.2 3.5x10 5 2x10 5

24. SiNANO Workshop, Montreux, Sept 2006 30% Terrace Graded Properties (MBE growth) High T growth + anneal y = 0.3 LG High T + anneal TG High T TDD (cm -2 ) PUD (cm -1 ) ~ 1.00 RMS roughness (nms) (20x20μm) ~ 53.2 3.5x10 5 2x10 5 + anneal  3x10 5  5x10 3

25. SiNANO Workshop, Montreux, Sept 2006 30% Terrace Graded Properties (MBE growth) Low T growth 800  700C y = 0.3 LG High T (850-790°C) TG High T TDD (cm -2 ) PUD (cm -1 ) ~ 1.00 RMS roughness (nms) (20x20μm) ~ 53.2 3.5x10 5 2x10 5 + anneal  3x10 5  5x10 3 TG Low T 3x10 3 0 1.9

26. SiNANO Workshop, Montreux, Sept 2006 ≈10 3 cm -2 TDD Pile-up < 0.1cm -1 30% TG TDD ≈ 3x10 3 cm -2 PUD = 0 TD

27. SiNANO Workshop, Montreux, Sept 2006 Terrace Grading – (SS-MBE) TDD for y  50% High T growth - 850  790C

28. SiNANO Workshop, Montreux, Sept 2006 Transfer to CVD TG virtual substrates up to y = 0.2 grown on ASM Epsilon 2000E™ RP-CVD reactor using SiH4, SiCl2H2 and GeH4 precursors. Optimisation work - growth temperatures, growth rates, strain gradients, no. of terraces, terrace widths, throughput, etc

29. SiNANO Workshop, Montreux, Sept 2006 Terrace Grading Properties (CVD) y→0.2 4 tiers

30. SiNANO Workshop, Montreux, Sept 2006 Terrace Grading Properties (CVD) y→0.2 Reciprocal space maps (000 and 220) of 2 tier TG 20% sample taken with XRD AFM images showing 10x10μm area and 2x2μm area Typical etch pit image of TG sample capped with 10nm of strained silicon. TDD ~ 10 5 TD

31. SiNANO Workshop, Montreux, Sept 2006 Pile-Up Free TG (2 tier) up to 17% (LPCVD) Measurements taken by Accent Optical Technologies 6x6 mm area Pile-up density: 0 Photoluminescence imageSurface image

32. SiNANO Workshop, Montreux, Sept 2006 Terrace Graded Props (CVD) y = 0.2 y = 0.2AdvanceSis Other Expert Assessment TDD (cm -2 )≈ 1x10 4 PUD (cm -1 )< 0.1 Relaxation (%)> 96 RMS roughness (nms) (20x20μm) < 1.8

33. SiNANO Workshop, Montreux, Sept 2006 Terrace Graded Props (CVD) y = 0.2 y = 0.2AdvanceSis Other Expert Assessment TDD (cm -2 )≈ 1x10 4 PUD (cm -1 )< 0.10.0 Relaxation (%)> 96 -- RMS roughness (nms) (20x20μm) < 1.81.65 1.1x10 5

34. SiNANO Workshop, Montreux, Sept 2006 Terrace Graded Props (CVD) y = 0.2 y = 0.2AdvanceSis Other Expert Assessment TDD (cm -2 )≈ 1x10 4 PUD (cm -1 )< 0.10.0 Relaxation (%)> 96 -- RMS roughness (nms) (20x20μm) < 1.81.65 1.1x10 5

35. SiNANO Workshop, Montreux, Sept 2006 Misfits at the sSi/VS interface MD TD

36. SiNANO Workshop, Montreux, Sept 2006 Misfits at the sSi/VS interface MD TD …….but t sSi = 10nm which is < t c (17nm)

37. SiNANO Workshop, Montreux, Sept 2006 EPD Reveal in VS with sSi layer Additional etch pit Strained silicon Virtual substrate TD MD TD Chemical etchant Etched surface  100% increase in EPD

38. SiNANO Workshop, Montreux, Sept 2006 Terrace Grading – basic studies (y→0.2) (with sSi layer)…CVD y Thickness (μm) 2 4 68 0.1 0.2 0.0 Number of terraces TDD (cm -2 ) Relaxation of upper terrace (%)

39. SiNANO Workshop, Montreux, Sept 2006 50% terrace graded (for sSi) TDD = 3x10 5 cm -2 PUD = 0

40. SiNANO Workshop, Montreux, Sept 2006 80% terrace graded (for sGe) TDD = 3x10 5 cm -2 PUD = 0

41. SiNANO Workshop, Montreux, Sept 2006 Terrace graded VSs – smoother! CMP LG data from LETI ….and no CMP

42. SiNANO Workshop, Montreux, Sept 2006 The Future Terrace grading Heralds a new generation in VS quality: eliminates pile-up low TDD potential to avoid CMP route to production√ Current work Examining new designs which directly manage the relaxation process: → thinner virtual substrates → TDD and PUD → zero → smooth enough for wafer bonding And finally Still a lot of parameter space to be explored – and if you thought Si-Ge relaxation was fully understood..….……

43. SiNANO Workshop, Montreux, Sept 2006 THINK AGAIN!

44. SiNANO Workshop, Montreux, Sept 2006 Linkage with SiNANO Many VS-based sSi layers supplied to WP1 and WP2 partners for device processing VSs characterised by partners VS-based sGe layers supplied to partner for device processing VS-based sSiGe and sGe layers to be supplied to Jeulich for OI bonding trials VS work enabled a presence on PULLNANO project

45. SiNANO Workshop, Montreux, Sept 2006 END