1. 1 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) CPRE 583 Reconfigurable Computing (VHDL Overview ) Instructor: Dr. Phillip Jones (phjones@iastate.edu) Reconfigurable Computing Laboratory Iowa State University Ames, Iowa, USA http://class.ece.iastate.edu/cpre583/

2. 2 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) VHDL basics VHDL: (V)HSIC (H)ardware (D)escription (L)anguage –VHSIC: (V)ery (H)igh (S)peed (I)ntegrated (C)ircuit It is NOT a programming language!!! It is a Hardware Description Language (HDL) Conceptually VERY different form C,C++

3. 3 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Some Key Differences from C C is inherently sequential (serial), one statement executed at a time VHDL is inherently concurrent (parallel), many statements execute (simulate) at a time

4. 4 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Some Key Differences from C C example VHDL example A = B + C X = Y + Z Ans = A + X Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X Current Values: A = 1 B = 1 C = 1 X = 1 Y = 1 Z = 1 Ans = 1 Current Values: A = 1 B = 1 C = 1 X = 1 Y = 1 Z = 1 Ans = 1

5. 5 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Some Key Differences from C C example VHDL example A = B + C X = Y + Z Ans = A + X Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X Current Values: A = 2 B = 1 C = 1 X = 1 Y = 1 Z = 1 Ans = 1 Current Values: A = 1 B = 1 C = 1 X = 1 Y = 1 Z = 1 Ans = 1

6. 6 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Some Key Differences from C C example VHDL example A = B + C X = Y + Z Ans = A + X Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 1 Current Values: A = 1 B = 1 C = 1 X = 1 Y = 1 Z = 1 Ans = 1

7. 7 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Some Key Differences from C C example VHDL example A = B + C X = Y + Z Ans = A + X Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 4 Current Values: A = 1 B = 1 C = 1 X = 1 Y = 1 Z = 1 Ans = 1

8. 8 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Some Key Differences from C C example VHDL example A = B + C X = Y + Z Ans = A + X Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 4 Current Values: A = 1 B = 1 C = 1 X = 1 Y = 1 Z = 1 Ans = 1 “Simulates in parallel ever delta time step” Show impact Of changing Order of statements

9. 9 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Some Key Differences from C C example VHDL example A = B + C X = Y + Z Ans = A + X Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 4 Current Values: A = 1 B = 1 C = 1 X = 1 Y = 1 Z = 1 Ans = 1 “Simulates in parallel ever delta time step” Snap shot after input change

10. 10 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Some Key Differences from C C example VHDL example A = B + C X = Y + Z Ans = A + X Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 4 Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 2 “Simulates in parallel ever delta time step”

11. 11 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Some Key Differences from C C example VHDL example A = B + C X = Y + Z Ans = A + X Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 4 Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 2 “Simulates in parallel ever delta time step” Different

12. 12 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Some Key Differences from C C example VHDL example A = B + C X = Y + Z Ans = A + X Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 4 Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 2 “Simulates in parallel ever delta time step” Snap shot after input change

13. 13 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Some Key Differences from C C example VHDL example A = B + C X = Y + Z Ans = A + X Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 4 Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 2 “Simulates in parallel ever delta time step”

14. 14 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Some Key Differences from C C example VHDL example A = B + C X = Y + Z Ans = A + X Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 4 Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 4 “Simulates in parallel ever delta time step”

15. 15 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Corresponding circuit VHDL example Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X “Simulates in parallel ever delta time step”

16. 16 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Corresponding circuit VHDL example Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X “Simulates in parallel ever delta time step” + + B(1) C(1) Y(1) Z(1) + A(1) X(1) Ans(1)

17. 17 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Corresponding circuit VHDL example Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X “Simulates in parallel ever delta time step” + + B(1) C(1) Y(1) Z(1) + A(2) X(2) Ans(2)

18. 18 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Corresponding circuit VHDL example Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X “Simulates in parallel ever delta time step” + + B(1) C(1) Y(1) Z(1) + A(2) X(2) Ans(4)

19. 19 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Corresponding circuit (More realistic) VHDL example Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C after 2ns X <= Y + Z after 2ns Ans <= A + X after 2ns “Simulates in parallel ever delta time step” + + B(1) C(1) Y(1) Z(1) + A(1) X(1) Ans(1) 2ns

20. 20 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) VHDL example Initially: A,B,C,X,Y,Z,Ans =1 “Simulates in parallel ever delta time step” + + B(1) C(1) Y(1) Z(1) + A(2) X(2) Ans(2) Corresponding circuit (More realistic) 2ns A <= B + C after 2ns X <= Y + Z after 2ns Ans <= A + X after 2ns

21. 21 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) VHDL example Initially: A,B,C,X,Y,Z,Ans =1 “Simulates in parallel ever delta time step” + + B(1) C(1) Y(1) Z(1) + A(2) X(2) Ans(4) Corresponding circuit (More realistic) 2ns A <= B + C after 2ns X <= Y + Z after 2ns Ans <= A + X after 2ns

22. 22 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Typical Structure of a VHDL File LIBRARY ieee; ENTITY test_circuit IS PORT(B,C,Y,Z,Ans); END test_circuit; ARCHITECTURE structure OF test_circuit IS signal A : std_logic_vector(7 downto 0); signal X : std_logic_vector(7 downto 0); BEGIN A <= B + C; X <= Y + Z; Ans <= A + X; END Include Libraries Define component name and Input/output ports Declare internal signals, components Implement components functionality

23. 23 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Process Process provide a level serialization in VHDL (e.g. variables, clocked processes) Help separate and add structure to VHDL design

24. 24 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Process Example BEGIN My_process_1 : process (A,B,C,X,Y,Z) Begin A <= B + C; X <= Y + Z; Ans <= A + X; End My_process_1; My_process_2 : process (B,X,Y,Ans1) Begin A <= B + 1; X <= B + Y; Ans2 <= Ans1 + X; End My_process_2; END; Sensitivity list: specify inputs to the process. Process is updated when a specified input changes

25. 25 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Process Example (Multiple Drivers) BEGIN My_process_1 : process (A,B,C,X,Y,Z) Begin A <= B + C; X <= Y + Z; Ans <= A + X; End My_process_1; My_process_2 : process (B,X,Y,Ans1) Begin A <= B + 1; X <= B + Y; Ans2 <= Ans1 + X; End My_process_2; END; A signal can only be Driven (written) by one process. But can be read by many Compile or simulator may give a “multiple driver” Error or Warning message

26. 26 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Process Example (Multiple Drivers) BEGIN My_process_1 : process (A,B,C,X,Y,Z) Begin A <= B + C; X <= Y + Z; Ans <= A + X; End My_process_1; My_process_2 : process (B,X,Y,Ans1) Begin A1 <= B + 1; X1 <= B + Y; Ans2 <= Ans1 + X; End My_process_2; END; Maybe A,X were suppose to be A1,X1. Cut and paste error. Or may need to rethink Hardware structure to remove multiple driver issue.

27. 27 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Process Example (if-statement) BEGIN My_process_1 : process (A,B,C,X,Y,Z) Begin if (B = 0) then C <= A + B; Z <= X + Y; Ans1 <= A + X; else C <= 1; Z <= 0; Ans1 <= 1; end if; End My_process_1; END; Add circuit

28. 28 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Clock Process Example BEGIN My_process_1 : process (clk) Begin IF (clk’event and clk = ‘1’) THEN C <= A or B; Z <= X or Y; Ans <= C and Z; END IF; End My_process_1; END; or A() B() X() Y() and C() Z() Ans() circuit not clocked

29. 29 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Clock Process Example BEGIN My_process_1 : process (clk) Begin IF (clk’event and clk = ‘1’) THEN C <= A or B; Z <= X or Y; Ans <= C and Z; END IF; End My_process_1; END; or A() B() X() Y() and C() Z() Ans() circuit with clock clk D Flip-Flop DFF Register

30. 30 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Clock Process Example BEGIN My_process_1 : process (clk) Begin IF (clk’event and clk = ‘1’) THEN C <= A or B; Z <= X or Y; Ans <= C and Z; END IF; End My_process_1; END; or A() B() X() Y() and C() Z() Ans() circuit with clock clk

31. 31 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Clock Process Example 2 BEGIN My_process_1 : process (clk) Begin IF (clk’event and clk = ‘1’) THEN C <= A xor B; Z <= X or Y; Ans <= C xor Z; END IF; End My_process_1; END; xor or A() B() X() Y() xor C() Z() Ans() circuit with clock clk

32. 32 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Clock Process Example 2 (Answer) BEGIN My_process_1 : process (clk) Begin IF (clk’event and clk = ‘1’) THEN C <= A xor B; Z <= X or Y; Ans <= C xor Z; END IF; End My_process_1; END; xor or A() B() X() Y() xor C() Z() Ans() circuit with clock clk

33. 33 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) VHDL Constructs Entity Process Signal, Variable, Constants, Integers Array, Record VHDL on-line tutorials: http://www.seas.upenn.edu/~ese201/vhdl/vhdl_primer.html http://www.vhdl-online.de/tutorial/

34. 34 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Signals and Variables Signals –Updated at the end of a process –Have file scope Variables –Updated instantaneously –Have process scope VHDL on-line tutorials: http://www.seas.upenn.edu/~ese201/vhdl/vhdl_primer.html http://www.vhdl-online.de/tutorial/

35. 35 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) std_logic, std_logic_vector Very common data types std_logic –Single bit value –Values: U, X, 0, 1, Z, W, H, L, - –Example: signal A : std_logic; A <= ‘1’; Std_logic_vector: is an array of std_logic –Example: signal A : std_logic_vector (4 downto 0); A <= x“00Z001” VHDL on-line tutorials: http://www.seas.upenn.edu/~ese201/vhdl/vhdl_primer.html http://www.vhdl-online.de/tutorial/

36. 36 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Std_logic values –U : Uninitialized (signal has not been assigned a value yet) –X : Unknow (2 drivers one ‘0’ one ‘1’) –H : weak ‘1’ (example: model pull-up resister) I have never used this value –L : weak ‘0’ Time step 0

37. 37 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Std_logic values –U : Uninitialized (signal has not been assigned a value yet) –X : Unknow (2 drivers one ‘0’ one ‘1’) –H : weak ‘1’ (example: model pull-up resister) I have never used this value –L : weak ‘0’ Time step 0 1 UUU Std_logic values

38. 38 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Std_logic values –U : Uninitialized (signal has not been assigned a value yet) –X : Unknow (2 drivers one ‘0’ one ‘1’) –H : weak ‘1’ (example: model pull-up resister) I have never used this value –L : weak ‘0’ Time step 1 0 1UU Std_logic values

39. 39 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Std_logic values –U : Uninitialized (signal has not been assigned a value yet) –X : Unknow (2 drivers one ‘0’ one ‘1’) –H : weak ‘1’ (example: model pull-up resister) I have never used this value –L : weak ‘0’ Time step 2 1 01U Std_logic values

40. 40 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Std_logic values –U : Uninitialized (signal has not been assigned a value yet) –X : Unknow (2 drivers one ‘0’ one ‘1’) –H : weak ‘1’ (example: model pull-up resister) I have never used this value –L : weak ‘0’ Time step 3 1 101 Std_logic values

41. 41 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Std_logic values –U : Uninitialized (signal has not been assigned a value yet) –X : Unknow (2 drivers one ‘0’ one ‘1’) –H : weak ‘1’ (example: model pull-up resister) I have never used this value –L : weak ‘0’ Time step 3 1 101 0 1 X Std_logic values

42. 42 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Std_logic values –U : Uninitialized (signal has not been assigned a value yet) –X : Unknow (2 drivers one ‘0’ one ‘1’) –H : weak ‘1’ (example: model pull-up resister) I have never used this value –L : weak ‘0’ Time step 3 1 101 0 1 X 1 0 Std_logic values

43. 43 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Std_logic values –U : Uninitialized (signal has not been assigned a value yet) –X : Unknow (2 drivers one ‘0’ one ‘1’) –H : weak ‘1’ (example: model pull-up resister) I have never used this value –L : weak ‘0’ Time step 3 1 11X 0 0 X 1 X Std_logic values

44. 44 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Std_logic values –U : Uninitialized (signal has not been assigned a value yet) –X : Unknow (2 drivers one ‘0’ one ‘1’) –H : weak ‘1’ (example: model pull-up resister) I have never used this value –L : weak ‘0’ Time step 0 ‘1’ Pull-up resistor Std_logic values

45. 45 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Std_logic values –U : Uninitialized (signal has not been assigned a value yet) –X : Unknow (2 drivers one ‘0’ one ‘1’) –H : weak ‘1’ (example: model pull-up resister) I have never used this value –L : weak ‘0’ Time step 0 0 U HU ‘1’ Pull-up resistor Std_logic values

46. 46 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Std_logic values –U : Uninitialized (signal has not been assigned a value yet) –X : Unknow (2 drivers one ‘0’ one ‘1’) –H : weak ‘1’ (example: model pull-up resister) I have never used this value –L : weak ‘0’ Time step 1 1 0 H1 ‘1’ Pull-up resistor Std_logic values

47. 47 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Std_logic values –U : Uninitialized (signal has not been assigned a value yet) –X : Unknow (2 drivers one ‘0’ one ‘1’) –H : weak ‘1’ (example: model pull-up resister) I have never used this value –L : weak ‘0’ Time step 2 0 1 01 ‘1’ Pull-up resistor Resolution(H,0) = 0 Std_logic values

48. 48 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) mysignal’event (mysignal changed value) mysignal’high (highest value of mysignal’s type) mysignal’low Many other attributes –http://www.cs.umbc.edu/help/VHDL/summary.htmlhttp://www.cs.umbc.edu/help/VHDL/summary.html Pre-defined VHDL attributes

49. 49 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Signal: global to file Variable: local to process Singal vs Varible scope VHDL on-line tutorials: http://www.seas.upenn.edu/~ese201/vhdl/vhdl_primer.html http://www.cs.umbc.edu/help/VHDL/summary.html http://www.vhdl-online.de/tutorial/ My_process_1 : process (B,C,Y) Begin A <= B + C; Z <= Y + C; End My_process_1; My_process_2 : process (B,X,Y,Ans1) Begin X <= Z + 1; Ans <= B + Y; End My_process_2;

50. 50 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Signal: global to file Variable: local to process Singal vs Varible scope VHDL on-line tutorials: http://www.seas.upenn.edu/~ese201/vhdl/vhdl_primer.html http://www.cs.umbc.edu/help/VHDL/summary.html http://www.vhdl-online.de/tutorial/ My_process_1 : process (B,C,Y) Begin A <= B + C; varZ <= Y + C; End My_process_1; My_process_2 : process (B,X,Y,Ans1) Begin X <= varZ + 1; Ans <= B + Y; End My_process_2; Each varZ are local to their process. Completely independent

51. 51 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Arrays and Records Arrays: Group signals of the same type together Records: Group signal of different types together VHDL on-line tutorials: http://www.seas.upenn.edu/~ese201/vhdl/vhdl_primer.html http://www.vhdl-online.de/tutorial/

52. 52 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Array Example (Delay Shift Register) VHDL on-line tutorials: http://www.seas.upenn.edu/~ese201/vhdl/vhdl_primer.html http://www.vhdl-online.de/tutorial/ flag_inflag_1flag_2flag_3 flag_out BEGIN My_process_1 : process (clk) Begin IF (clk’event and clk = ‘1’) THEN flag_1 <= flag_in; flag_2 <= flag_1; flag_3 <= flag_2; END IF; End My_process_1; flag_out <= flag_3 END;

53. 53 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Array Example (Delay Shift Register) flag_inflag_1flag_20 flag_out BEGIN My_process_1 : process (clk) Begin IF (clk’event and clk = ‘1’) THEN flag_reg(flag_reg'high downto 0) <= flag_reg(flag_reg'high-1 downto 0) & flag_in; END IF; End My_process_1; flag_out <= flag_reg(flag_reg'high); END; type flag_reg_array is array (DELAY-1 downto 0) of std_logic; signal flag_reg : flag_reg_array;

54. 54 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Array Example (Delay Shift Register) VHDL on-line tutorials: http://www.seas.upenn.edu/~ese201/vhdl/vhdl_primer.html http://www.vhdl-online.de/tutorial/ flag_inflag_1flag_20 flag_out BEGIN My_process_1 : process (clk) Begin IF (clk’event and clk = ‘1’) THEN flag_1 <= flag_in; flag_2 <= flag_1; flag_20 <= flag_19; END IF; End My_process_1; flag_out <= flag_20 END;

55. 55 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Array Example (Delay Shift Register) flag_reg(flag_reg'high downto 0)<= flag_reg(flag_reg'high-1 downto 0) & flag_in; flag_inflag(0)flag(1)flag(2) flag_out 001 1 flag_inflag(0)flag(1)flag(2) flag_out 100 flag_inflag(0)flag(1)flag(2) flag_out 001 1

56. 56 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Array Example (Delay Shift Register) VHDL on-line tutorials: http://www.seas.upenn.edu/~ese201/vhdl/vhdl_primer.html http://www.vhdl-online.de/tutorial/ flag_inflag_0flag_1flag_2 flag_out BEGIN My_process_1 : process (clk) Begin IF (clk’event and clk = ‘1’) THEN flag_1 <= flag_in; flag_2 <= flag_1; flag_3 <= flag_2; END IF; End My_process_1; flag_out <= flag_3 END;

57. 57 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Finite State Machine (FSM) Design Model of computation High level application example (Networking) Two major types –Moore –Mealy Detailed view of application example

58. 58 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Finite State Machines What types of applications are they well suited –Streaming pattern recognition –Sequential event based control logic Allow hardware designer to reason about things in small pieces

59. 59 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Streaming Network application (MP1) Process UDP packet headers (event driven) Detect patterns in payload (e.g. “Corn”) Modify payload based on header information FSM

60. 60 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Streaming Network application (MP1) Process UDP packet headers (event driven) Detect patterns in payload (e.g. “Corn”) Modify payload based on header information FSM IP src

61. 61 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Streaming Network application (MP1) Process UDP packet headers (event driven) Detect patterns in payload (e.g. “Corn”) Modify payload based on header information FSM IP destIP src

62. 62 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Streaming Network application (MP1) Process UDP packet headers (event driven) Detect patterns in payload (e.g. “Corn”) Modify payload based on header information FSM src portIP destIP src

63. 63 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Streaming Network application (MP1) Process UDP packet headers (event driven) Detect patterns in payload (e.g. “Corn”) Modify payload based on header information FSM dest portsrc portIP destIP src

64. 64 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Streaming Network application (MP1) Process UDP packet headers (event driven) Detect patterns in payload (e.g. “Corn”) Modify payload based on header information FSM lengthdest portsrc portIP destIP src

65. 65 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Streaming Network application (MP1) Process UDP packet headers (event driven) Detect patterns in payload (e.g. “Corn”) Modify payload based on header information FSM Data 1lengthdest portsrc portIP destIP src

66. 66 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Streaming Network application (MP1) Process UDP packet headers (event driven) Detect patterns in payload (e.g. “Corn”) Modify payload based on header information FSM Data 2Data 1lengthdest portsrc portIP destIP src

67. 67 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Streaming Network application (MP1) Process UDP packet headers (event driven) Detect patterns in payload (e.g. “Corn”) Modify payload based on header information FSM Data 3Data 2Data 1lengthdest portsrc portIP dest

68. 68 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Streaming Network application (MP1) Process UDP packet headers (event driven) Detect patterns in payload (e.g. “Corn”) Modify payload based on header information FSM Send Alert Data 3Data 2Data 1lengthdest portsrc portIP dest

69. 69 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Streaming Network application (MP1) Process UDP packet headers (event driven) Detect patterns in payload (e.g. “Corn”) Modify payload based on header information FSM Send Alert roClengthdest portsrc portIP dest

70. 70 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Streaming Network application (MP1) Process UDP packet headers (event driven) Detect patterns in payload (e.g. “Corn”) Modify payload based on header information FSM Send Alert nroClengthdest portsrc port

71. 71 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Alert!! Streaming Network application (MP1) Process UDP packet headers (event driven) Detect patterns in payload (e.g. “Corn”) Modify payload based on header information FSM Send Alert !nroClengthdest port

72. 72 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Streaming Network application (MP1) Process UDP packet headers (event driven) Detect patterns in payload (e.g. “Corn”) Modify payload based on header information FSM Send Alert Modify Packet !nroClengthdest port

73. 73 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Moore and Mealy FSMs Moore: Output is only a function of the current state Mealy: Output is a function of the current state and input (“Mealy is more”)

74. 74 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Moore FSM Moore: Output is only a function of the current state Example detect every occurrence of “1011” Start (0) 1 (0) 11 (0) 011 (0) 1011 (1) State Name FSM output

75. 75 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Moore FSM Moore: Output is only a function of the current state Example detect every occurrence of “1011” Start (0) 1 (0) 11 (0) 011 (0) 1011 (1) 1 0 Where to go on a given input

76. 76 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Moore FSM Moore: Output is only a function of the current state Example detect every occurrence of “1011” Start (0) 1 (0) 11 (0) 011 (0) 1011 (1) 1 0 Input: 1 Output: 0

77. 77 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Moore FSM Moore: Output is only a function of the current state Example detect every occurrence of “1011” Start (0) 1 (0) 11 (0) 011 (0) 1011 (1) 1 0 Input: 11011 1 0 1 0 1 0 0 1 Output: 00010

78. 78 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Moore FSM Moore: Output is only a function of the current state Example detect every occurrence of “1010” Start (0) 0 (0) 0 1 10 (0) 1 010 (0) 0 1010 (1) 1 1 0 1 1 0 0

79. 79 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Mealy FSM Moore: Output a function of the current state, and input Example detect every occurrence of “1011” 1110111011 State Name

80. 80 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Mealy FSM 1/0 0/0 1110111011 Input output Moore: Output a function of the current state, and input Example detect every occurrence of “1011” Start

81. 81 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Mealy FSM 1/0 0/0 1110111011 Mealy: Output a function of the current state, and input Example detect every occurrence of “1011” 1/0 0/0 1/1 0/0 Start 1/0

82. 82 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Let: –X be inputs –Z be outputs –State(t) be the state of the FSM at the current time –State(t+1) be the next state of the FSM –δ be the transition between states State(t+1) = δ(State(t), X) Output –Moore: Z(State(t)) –Mealy: Z(State(t), X) FSM: General Circuit Architecture x=1/z=0 0/1 S1S2 1/0 0/0 z=0

83. 83 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) FSM: General Circuit Architecture Combinational Logic Inputs: X Z(State(t)) Z(State(t),X) Outputs Moore Mealy State Storage DFF State(t) State(t+1) = δ(State(t), X) Next State

84. 84 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) VHDL: IF and CASE constructs IF THEN ELSE can be mapped to a 2:1 Multiplexer (Mux) 2:1 Mux sel = b“0” 4 4 4 x”C” x”D” in_0 in_1 x”C” IF (sel = ‘0’) THEN out_1 <= in_0; ELSE out_1 <= in_1 END IF; out_1

85. 85 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) VHDL: IF and CASE constructs 4:1 Mux sel = b“10” 4 4 4 4 2 4 x”C” x”D” x”2” x”7” in_0 in_1 in_2 in_3 x”7” Mapping a CASE statement to a 4:1 Mux out_1 CASE sel is WHEN “00” => out_1 <= in_0; WHEN “01” => out_1 <= in_1; WHEN “10” => out_1 <= in_2; WHEN “11” => out_1 <= in_3 WHEN OTHERS => out_1 <= in_0; END CASE; Why do we need others here?

86. 86 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) CASE state is WHEN state_1 => IF (sel = ‘0’) THEN mux_out <= ‘1’; ELSE mux_out <= ‘0’; END IF; WHEN state_11 => -- similar code WHEN state_011 => IF (sel = ‘0’) THEN mux_out <= ‘0’; ELSE mux_out <= ‘1’; WHEN state_1011 => --similar code END CASE; VHDL: IF and CASE constructs State = {state_1, state_11, state_011, state_1011} = {“00”, ”01”, ”10”, ”11”} Enumerated Type Mapping a CASE statement to a 1:4 Decoder 1:4 Decoder 2 out_0 out_1 out_2 out_3 state “10” on 2:1 Mux off 2:1 Mux off 2:1 Mux off 2:1 Mux

87. 87 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) CASE state is WHEN state_1 => IF (sel = ‘0’) THEN mux_out <= ‘1’; ELSE mux_out <= ‘0’; END IF; WHEN state_11 => -- similar code WHEN state_011 => IF (sel = ‘0’) THEN mux_out <= ‘0’; ELSE mux_out <= ‘1’; WHEN state_1011 => --similar code END CASE; VHDL: IF and CASE constructs State = {state_1, state_11, state_011, state_1011} = {“00”, ”01”, ”10”, ”11”} Enumerated Type Mapping a CASE statement to a 1:4 Decoder 1:4 Decoder 2 out_0 out_1 out_2 out_3 state “00” on 2:1 Mux off 2:1 Mux off 2:1 Mux off 2:1 Mux

88. 88 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) FSM: General Circuit Architecture Combinational Logic Inputs: X Z(State(t)) Z(State(t),X) Outputs Moore Mealy State Storage DFF State(t) State(t+1) = δ(State(t), X) Next State

89. 89 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) -- Store the “state” Update_State: process(clk) begin if(clk’event and clk=‘1’) then state <= next_state; end if; end process Update_State; VHDL for Mealy (“1011”) Example DFF next_state state

90. 90 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) -- Compute combinational logic Combinational: process(x, state) begin case state is when state_1 => if(x = ‘0’) then z <= ‘0‘; next_state <= state_1; else z <= ‘0‘; next_state <= state_11; end if; when state_11 => if(x = ‘0’) then z <= ‘0’; next_state <= state_1; else z <= ‘0‘; next_state <= state_011 ; end if; VHDL for Mealy (“1011”) Example 1/0 0/0 1110111011 1/0 0/0 1/1 0/0 Start 1/0 Compute output Compute next_state

91. 91 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) when state_011 => if(x = ‘0’) then z <= ‘0‘; next_state <= state_1011; else z <= ‘0‘; next_state <= state_011; end if; when state_1011 => if(x = ‘0’) then z <= ‘0’; next_state <= state_1; else z <= ‘1‘; next_state <= state_11; end if; end case; end process Combinational; VHDL for Mealy (“1011”) Example 1/0 1110111011 1/0 0/0 1/1 0/0 1/0

92. 92 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Network Processing Example: UDP UDP – User Datagram Protocol –Popular protocol for sending data over the internet (TCP is popular another protocol) –Typical encapsulated within IP (Internet Protocol) UDP/IP –Gives no guarantee of delivery Relies on application layer to implement reliability Unlike TCP which has reliably delivery build in. Reference for more info on IP and UDP details –http://www.freesoft.org/CIE/http://www.freesoft.org/CIE/ RCFs Course

93. 93 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) UDP/IP Packet Format VerIHLTOSTotal Length Identificationflagsfragment offset TTLProtocolHeader Checksum Source IP Address Destination IP Address PaddingOptions Note: flags 3 bits 32-bits IP Header Source PortDestination Port LengthChecksum UDP Header Byte1 UDP length (bytes) = UDP header+payload 0 31 Byte2Byte3Byte4 UDP Protocol = 17 Payload

94. 94 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Raise an alert signal when the pattern “corn!” is detected Return the number of times “corn!” is detected –Place count value as the last byte of the payload Example: Network Processing Tasks

95. 95 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Streaming Network application (MP1) Detect patterns in payload (e.g. “Corn!”) Place the number of detections in last byte of payload FSM Send Alert Modify Packet !nroClengthdest port

96. 96 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Architecture Alert FSM Alert Register & Counter Management Packet Input Process Packet Output Process 2:1 Mux corn_cnt output sel Detect patterns in payload (e.g. “Corn!”) Place the number of detections in last byte of payload position Packet Length Draw out logic, and data flow!!!

97. 97 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Architecture Alert FSM Alert Register & Counter Management Packet Input Process Packet Output Process 2:1 Mux corn_cnt output sel Detect patterns in payload (e.g. “Corn!”) Place the number of detections in last byte of payload position Packet Length

98. 98 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Alert signal when the pattern “corn!” is detected –Z = {Alert} Alert FSM Design “c”/0 corn “o”/0 “r”/0 Start ! “n”/0 “!”/1 others/0

99. 99 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Alert signal when the pattern “corn!” is detected Output Packet’s Length –Z = {Alert,length_vld,pack_length} –X = {vld,input} : Note “?” is don’t care Alert FSM Design “c”/0 corn “o”/0 “r”/0 Start ! “n”/0 “!”/1 others/0

100. 100 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Alert signal when the pattern “corn!” is detected Output Packet’s Length –Z = {Alert,length_vld,pack_length} –X = {vld,input} : Note “?” is don’t care Alert FSM Design 1,“c”/0,0,0 corn 1,“o”/0,0,0 1,“r”/0,0,0 Start ! 1,“n”/0,0,0 1,“!”/1,0,0 1,others/0,0,0 Start IP IPH_2 1,”?”/0,0,0 IPH_5 1,”?”/0,0,0 UDP ports UDP length 1,”?”/0,0,0 1,”?”/0,1,length

101. 101 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Architecture Alert FSM Alert Register & Counter Management Packet Input Process Packet Output Process 2:1 Mux corn_cnt output sel Detect patterns in payload (e.g. “Corn!”) Place the number of detections in last byte of payload position Packet Length

102. 102 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Register & Counter Components Design of Manager Register & Counter Manager

103. 103 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Register and Counter Components 4:1 Mux DFF 8 count + 8 8 Counter inc_val 0 set_value sel(reset,load,inc) reset load inc 3:1 Mux DFF 8 reg_val 8 Register 0 set_value sel(reset,load) reset load

104. 104 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Practice: Write VHDL(process for each) 4:1 Mux DFF 8 count + 8 8 Counter inc_val 0 set_value sel(reset,load,inc) reset load inc 3:1 Mux DFF 8 reg_val 8 Register 0 set_value sel(reset,load) reset load CASE sel is WHEN “00” | “11”=> out_1 <= in_0; WHEN “01” => out_1 <= in_1; WHEN OTHERS => out_1 <= in_0; END CASE; Name : process(clk) begin if(clk’event and clk=‘1’) then logic here end if; end process Name

105. 105 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Register VHDL 3:1 Mux DFF 8 reg_val 8 Register 0 set_value sel(reset,load) reset load Name : process(clk) begin if(clk’event and clk=‘1’) then CASE reset&load is WHEN “10” | “11” => reg_val <= 0; WHEN “01” => reg_val <= set_value; WHEN OTHERS => reg_val <= reg_val; END CASE; end if; end process Name

106. 106 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Register VHDL 3:1 Mux DFF 8 reg_val 8 Register 0 set_value sel(reset,load) reset load Name : process(clk) begin if(clk’event and clk=‘1’) then CASE sel is WHEN “10” | “11” => reg_val <= 0; WHEN “01” => reg_val <= set_value; WHEN OTHERS => reg_val <= reg_val; END CASE; end if; end process Name sel <= reset&load;

107. 107 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Counter VHDL Name : process(clk) begin if(clk’event and clk=‘1’) then CASE reset&load&inc is WHEN “100” | “101” | “110”| “111” => count <= 0; WHEN “010” | “011” => count <= set_value; WHEN “001” => count <= count + inc_val; WHEN OTHERS => count <= count; END CASE; end if; end process Name 4:1 Mux DFF 8 count + 8 8 Counter inc_val 0 set_value sel(reset,load,inc) reset load inc

108. 108 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Counter VHDL Name : process(clk) begin if(clk’event and clk=‘1’) then CASE sel is WHEN “100” | “101” | “110”| “111” => count <= 0; WHEN “010” | “011” => count <= set_value; WHEN “001” => count <= count + inc_val; WHEN OTHERS => count <= count; END CASE; end if; end process Name sel <= reset&load&inc; 4:1 Mux DFF 8 count + 8 8 Counter inc_val 0 set_value sel(reset,load,inc) reset load inc

109. 109 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Architecture Alert FSM Alert Register & Counter Management Packet Input Process Packet Output Process 2:1 Mux corn_cnt output sel Detect patterns in payload (e.g. “Corn!”) Place the number of detections in last byte of payload position Packet Length

110. 110 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Register and Counter Manger Alert Packet_Length length_vld corn_cnt Packet_Length_reg Counter reset inc reset load Register 0 set_value 0 load reset inc_val 1 Counter inc reset load 0 set_value 0 inc_val 1 position Valid_data

111. 111 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Architecture Alert FSM Alert Register & Counter Management Packet Input Process Packet Output Process 2:1 Mux corn_cnt output sel Detect patterns in payload (e.g. “Corn!”) Place the number of detections in last byte of payload position Packet Length length_vld reset data_vld data reset Packet_length

112. 112 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Architecture Alert FSM Alert Register & Counter Management Packet Input Process Packet Output Process 2:1 Mux corn_cnt output sel Detect patterns in payload (e.g. “Corn!”) Place the number of detections in last byte of payload position Packet Length length_vld reset data_vld data reset Packet_length

113. 113 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Output sel 2:1 Mux Data_from_input corn_cnt 1 0 Data_to_output sel Comparator Packet_length Position Comparator outputs 1 if inputs match

114. 114 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Output sel: VHDL 2:1 Mux Data_from_input corn_cnt 1 0 Data_to_output sel Comparator Packet_length Position Comparator outputs 1 if inputs match NOT in a process! Data_to_output <= corn_cnt when (Packet_length = Position) else Data_from_input

115. 115 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Architecture Alert FSM Alert Register & Counter Management Packet Input Process Packet Output Process 2:1 Mux corn_cnt output sel Detect patterns in payload (e.g. “Corn!”) Place the number of detections in last byte of payload position Packet Length length_vld reset data_vld data reset Packet_length

116. 116 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Multiple Characters per Clock Network input stream typically 32-bit words –4 8-bit characters per word. corn! Example corn !? ?? Word 1 Word 2 corn Start !??? corn/0 others/0 !???/1 Corn! on a word boundary

117. 117 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Multiple Characters per Clock Network input stream typically 32-bit words –4 8-bit characters per word. corn! Example ?cor n! ?? Word 1 Word 2 ?cor Start n!?? ?cor/0 others/0 n!??/1 Corn! offset by 1 byte

118. 118 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Multiple Characters per Clock Network input stream typically 32-bit words –4 8-bit characters per word. corn! Example ??co rn !? Word 1 Word 2 ??co Start rn!? ??co/0 others/0 rn!/1 Corn! offset by 2 bytes

119. 119 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Multiple Characters per Clock Network input stream typically 32-bit words –4 8-bit characters per word. corn! Example ???c or n! Word 1 Word 2 ???c Start orn! ???c/0 others/0 orn!/1 Corn! offset by 3 bytes

120. 120 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Multiple Characters per Clock Network input stream typically 32-bit words –4 8-bit characters per word. corn! Example corn !? ?? Word 2 Word 3 corn Start !??? corn/0 others/0 !???/1 Corn! offset by 4 bytes

121. 121 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Modify Alert FSM for Multiple characters Start

122. 122 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Modify Alert FSM for Multiple characters corn!??? corn/0 others/0 !???/1 ?corn!?? ?cor/0 others/0 n!??/1 ??corn!? ??co/0 others/0 rn!/1 ???corn! ???c/0 others/0 orn!/1 Start

123. 123 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Modify Alert FSM for Multiple characters corn!??? corn/0 others/0 !???/1 ?corn!?? ?cor/0 others/0 n!??/1 ??corn!? ??co/0 others/0 rn!/1 ???corn! ???c/0 others/0 orn!/1 Start

124. 124 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Modify Alert FSM for Multiple characters corn!??? corn/0 others/0 !???/1 ?cor n!?? ?cor/0 others/0 n!??/1 ??corn!? ??co/0 others/0 rn!?/1 ???corn! ???c/0 others/0 orn!/1 Start

125. 125 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Modify Alert FSM for Multiple characters corn!??? corn/0 others/0 !???/1 ?cor n!?? ?cor/0 others/0 n!??/1 ??corn!? ??co/0 others/0 rn!?/1 ???corn! ???c/0 others/0 orn!/1 Start cbco rn!c orn! zcor

126. 126 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Modify Alert FSM for Multiple characters corn!??? corn/0 others/0 !???/1 ?cor n!?? ?cor/0 others/0 n!??/1 ??corn!? ??co/0 others/0 rn!?/1 ???corn! ???c/0 others/0 orn!/1 Start cbco rn!c orn! zcor

127. 127 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Modify Alert FSM for Multiple characters corn!??? corn/0 others/0 !???/1 ?cor n!?? ?cor/0 others/0 n!??/1 ??corn!? ??co/0 others/0 rn!?/1 ???corn! ???c/0 others/0 orn!/1 Start cbco rn!c orn! zcor

128. 128 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Modify Alert FSM for Multiple characters corn!??? corn/0 others/0 !???/1 ?cor n!?? ?cor/0 others/0 n!??/1 ??corn!? ??co/0 others/0 rn!?/1 ???corn! ???c/0 others/0 orn!/1 Start cbco rn!c orn! zcor

129. 129 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Modify Alert FSM for Multiple characters corn!??? corn/0 others/0 !???/1 ?cor n!?? ?cor/0 others/0 n!??/1 ??corn!? ??co/0 others/0 rn!?/1 ???corn! ???c/0 others/0 orn!/1 Start cbco rn!c orn! zcor

130. 130 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Modify Alert FSM for Multiple characters corn!??? corn/0 others/0 !???/1 ?cor n!?? ?cor/0 others/0 n!??/1 ??corn!? ??co/0 others/0 rn!?/1 ???corn! ???c/0 others/0 orn!/1 Start cbco rn!c orn! zcor

131. 131 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Modify Alert FSM for Multiple characters corn!??? corn/0 others/0 !???/1 ?cor n!?? ?cor/0 others/0 n!??/1 ??corn!? ??co/0 others/0 rn!?/1 ???corn! ???c/0 others/0 orn!/1 Start cbco rn!c orn! zcor

132. 132 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Modify Alert FSM for Multiple characters corn!??? corn/0 others/0 !???/1 ?cor n!?? ?cor/0 others/0 n!??/1 ??corn!? ??co/0 others/0 rn!?/1 ???corn! ???c/0 others/0 orn!/1 Start cbco rn!c orn! zcor

133. 133 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Modify Alert FSM for Multiple characters corn!??? corn/0 others/0 !???/1 ?cor n!?? ?cor/0 others/0 n!??/1 ??corn!? ??co/0 others/0 rn!?/1 ???corn! ???c/0 others/0 orn!/1 Start cbco rn!c orn! zcor

134. 134 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Modify Alert FSM for Multiple characters corn!??? corn/0 others/0 !???/1 ?cor n!?? ?cor/0 others/0 n!??/1 ??corn!? ??co/0 others/0 rn!?/1 ???corn! ???c/0 others/0 orn!/1 Start cbco rn!c orn! zcor

135. 135 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Modify corn! counter for Multiple characters Alert corn_cnt Counter reset inc reset load 0 set_value 0 inc_val 1

136. 136 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Modify corn! counter for Multiple characters Alt_0 corn_cnt Counter reset inc reset load 0 set_value 0 inc_val 1 Alt_1 Alt_2 Alt_3

137. 137 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Modify corn! counter for Multiple characters Alt_0 corn_cnt Counter reset inc reset load 0 set_value 0 inc_val 1 Alt_1 Alt_2 Alt_3 OR

138. 138 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Modify corn! counter for Multiple characters Alt_0 corn_cnt Counter reset inc reset load 0 set_value 0 inc_val Alt_1 Alt_2 Alt_3 OR 4:1 Mux sel(Alt0,Alt1, Alt2,Alt3) 4 3 2 1 NOT in a process! Alt_merge <= Alt0 & Alt1 & Alt2 & Alt3; inc_val <= 4 when (Alt_merge = “1111”) 3 when (Alt_merge = “0111” or Alt_merge = “1011”...) 2 when (Alt_merge = “0011” or Alt_merge = “0110”...) else 0

139. 139 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Modify corn! counter for Multiple characters Alt_0 corn_cnt Counter reset inc reset load 0 set_value 0 inc_val 1 Alt_1 Alt_2 Alt_3 OR

140. 140 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) In progress Slides

141. 141 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Moore FSM Moore: Output is only a function of the current state Example detect every occurrence of “1011” Start (0) 1 (0) 11 (0) 011 (0) 1011 (1) State Name FSM output

142. 142 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Moore FSM Moore: Output is only a function of the current state Example detect every occurrence of “1011” Start (0) 1 (0) 11 (0) 011 (0) 1011 (1) 1 0 Where to go on a given input

143. 143 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Moore FSM Moore: Output is only a function of the current state Example detect every occurrence of “1011” Start (0) 1 (0) 11 (0) 011 (0) 1011 (1) 1 0 Input: 1

144. 144 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Moore FSM Moore: Output is only a function of the current state Example detect every occurrence of “1011” Start (0) 1 (0) 11 (0) 011 (0) 1011 (1) 1 0 1 Input: 11 0

145. 145 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Moore FSM Moore: Output is only a function of the current state Example detect every occurrence of “1011” Start (0) 1 (0) 11 (0) 011 (0) 1011 (1) 1 0 1 0 Input: 011 0 1 0

146. 146 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Moore FSM Moore: Output is only a function of the current state Example detect every occurrence of “1011” Start (0) 1 (0) 11 (0) 011 (0) 1011 (1) 1 0 Input: 1011 1 0 1 0 0 1

147. 147 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Moore FSM Moore: Output is only a function of the current state Example detect every occurrence of “1011” Start (0) 1 (0) 11 (0) 011 (0) 1011 (1) 1 0 Input: 01011 1 0 1 0 0 0 1

148. 148 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Moore FSM Moore: Output is only a function of the current state Example detect every occurrence of “1011” Start (0) 1 (0) 11 (0) 011 (0) 1011 (1) 1 0 Input: 11011 1 0 1 0 1 0 0 1

149. 149 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Moore FSM Moore: Output is only a function of the current state Example: vending machine –Events (assume all items cost 1 coin): Insert Coin Make selection Start (0) Coin (0) Insert Coin Snack (1) Make selection Insert Coin Make selection Return (0) Insert Coin Make selection

150. 150 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Moore FSM Moore: Output is only a function of the current state Example: vending machine –Events (assume all items cost 1 coin): Insert Coin Make selection Return Coin Start (0) Coin (0) Insert Coin Snack (1) Make selection Insert Coin Make selection Return (0) Return Coin

151. 151 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Moore FSM Moore: Output is only a function of the current state Example: vending machine –Events (assume all items cost 1 coin): Insert Coin Make selection Return Coin Start (0) Coin (0) Insert Coin Snack (1) Make selection Insert Coin Make selection Return (0) Return Coin Make selection Return coin Insert Coin Return Coin

152. 152 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Moore FSM Moore: Output is only a function of the current state Example: vending machine –Events (assume all items cost 1 coin): Insert Coin Make selection Start (0) Coin (0) Insert Coin Snack (1) Make selection Insert Coin Make selection Return (0) Insert Coin Make selection Make Coin a snack option