1. BMayer@ChabotCollege.edu ENGR-43_Lec-05-3b_Thevein-Norton_Part-b.ppt 1 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Bruce Mayer, PE Licensed Electrical & Mechanical Engineer BMayer@ChabotCollege.edu Engineering 43 MaxPower SuperPosition

2. BMayer@ChabotCollege.edu ENGR-43_Lec-05-3b_Thevein-Norton_Part-b.ppt 2 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Thevénin’s Equivalence Theorem  Thevenin Equivalent Circuit for PART A  v TH = Thévenin Equivalent VOLTAGE Source  R TH = Thévenin Equivalent SERIES RESISTANCE

3. BMayer@ChabotCollege.edu ENGR-43_Lec-05-3b_Thevein-Norton_Part-b.ppt 3 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Norton’s Equivalence Theorem  Norton Equivalent Circuit for PART A  i N = Norton Equivalent CURRENT Source  R N = Norton Equivalent PARALLEL RESISTANCE

4. BMayer@ChabotCollege.edu ENGR-43_Lec-05-3b_Thevein-Norton_Part-b.ppt 4 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Maximum Power Transfer  Consider The Amp-Speaker Matching Issue From PreAmp (voltage ) To speakers

5. BMayer@ChabotCollege.edu ENGR-43_Lec-05-3b_Thevein-Norton_Part-b.ppt 5 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Maximum Power Xfer Cont  The Simplest Model for a Speaker is to Consider it as a RESISTOR only  Since the “Load” Does the “Work” We Would like to Transfer the Maximum Amount of Power from the “Driving Ckt” to the Load Anything Less Results in Lost Energy in the Driving Ckt in the form of Heat BASIC MODEL FOR THE ANALYSIS OF POWER TRANSFER

6. BMayer@ChabotCollege.edu ENGR-43_Lec-05-3b_Thevein-Norton_Part-b.ppt 6 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Maximum Power Transfer  Consider Thevenin Equivalent Ckt with Load R L  Find Load Pwr by V-Divider  For every choice of R L we have a different power. How to find the MAXIMUM Power value?  Consider P L as a FUNCTION of R L and find the maximum of such a function  have at left! i.e., Take 1 st Derivative and Set to Zero

7. BMayer@ChabotCollege.edu ENGR-43_Lec-05-3b_Thevein-Norton_Part-b.ppt 7 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Max Power Xfer cont  Find Max Power Condition Using Differential Calculus  Set The Derivative To Zero To Find MAX or MIN Points For this Case Set To Zero The NUMERATOR  Solving for “Best” (P max ) Load  This is The Maximum Power Transfer Theorem The load that maximizes the power transfer for a circuit is equal to the Thevenin equivalent resistance of the circuit

8. BMayer@ChabotCollege.edu ENGR-43_Lec-05-3b_Thevein-Norton_Part-b.ppt 8 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Max Power Quantified  By Calculus we Know R L for P L,max  Recall the Power Transfer Eqn  Sub R TH for R L  So Finally

9. BMayer@ChabotCollege.edu ENGR-43_Lec-05-3b_Thevein-Norton_Part-b.ppt 9 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Max Pwr Xfer Example  Determine R L for Maximum Power Transfer  Need to Find R TH Notice This Ckt Contains Only INDEPENDENT Sources  Thus R TH By Source Deactivation  This is Then the R L For Max Power Transfer  To Find the AMOUNT of Power Transferred Need the Thevenin Voltage  Then use R TH = 6kΩ along with V TH ab

10. BMayer@ChabotCollege.edu ENGR-43_Lec-05-3b_Thevein-Norton_Part-b.ppt 10 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Max Pwr Xfer Example cont  To Find V TH Use Meshes  The Eqns for Loops 1 & 2  Solving for I 2  Now Apply KVL for V OC  Recall  At Max: P L = P MX, R L = R TH

11. BMayer@ChabotCollege.edu ENGR-43_Lec-05-3b_Thevein-Norton_Part-b.ppt 11 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Max Pwr Xfer  Determine R L and Max Power Transferred  Find Thevenin Equiv. At This Terminal-Set  Recall for Max Pwr Xfer a b  This is a MIXED Source Circuit Analysis Proceeds More Quickly if We start at c-d and Adjust for the 4kΩ at the end c d  Use Loop Analysis  Eqns for Loops 1 & 2

12. BMayer@ChabotCollege.edu ENGR-43_Lec-05-3b_Thevein-Norton_Part-b.ppt 12 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Max Pwr Xfer cont  The Controlling Variable  Now Short Ckt Current The Added Wire Shorts the 2k Resistor  Remember now the partition points  Then R TH c d  The R TH for ckt at a-b = 2kΩ+4kΩ; So a b

13. BMayer@ChabotCollege.edu ENGR-43_Lec-05-3b_Thevein-Norton_Part-b.ppt 13 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Thevenin & Norton Summary  Independent Sources Only R TH = R N by Source Deactivation V TH –= V OC or –= R N ·I SC I N –= I SC or –= V OC /R TH  Mixed INdep and Dep Srcs Must Keep Indep & dep Srcs Together in Driving Ckt V TH = V OC I N = I SC R TH = R N = V OC / I SC  DEPENDENT Sources Only Must Apply V or I PROBE –Pick One, say I P = 1.00 mA, then Calculate the other, say V P V TH = I N = 0 R TH = R N = V P / I P

14. BMayer@ChabotCollege.edu ENGR-43_Lec-05-3b_Thevein-Norton_Part-b.ppt 14 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis WhiteBoard Work LLet’s Work this nice Problem FFind P max for Load R L

15. BMayer@ChabotCollege.edu ENGR-43_Lec-05-3b_Thevein-Norton_Part-b.ppt 15 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Previous Equivalent Circuits   [Independent Srcs] V src ’s in Series I src ’s in Parallel  Series & Parallel Resistors  The Complementary Configs are Inconsistent with Source Definitions

16. BMayer@ChabotCollege.edu ENGR-43_Lec-05-3b_Thevein-Norton_Part-b.ppt 16 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Linearity  Models Used So Far Are All LINEAR Mathematically This Implies That They satisfy the principle of SUPERPOSITION  The Model T(u) is Linear IF AND ONLY IF For All Possible –Input Pairs: u 1 & u 2 –Scalars α 1 & α 2  AN Alternative, And Equivalent, Linearity & Superposition Definition The Model T(u) is Linear IF AND ONLY IF It Exhibits –ADDITIVITY –HOMOGENEITY

17. BMayer@ChabotCollege.edu ENGR-43_Lec-05-3b_Thevein-Norton_Part-b.ppt 17 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Linearity cont.  Linearity Characteristics Additivity  NOTE Technically, Linearity Can Never Be Verified Empirically on a System But It Could Be Disproved by a SINGLE Counter Example. It Can Be Verified Mathematically For The Models Used Homogeneity –a.k.a. Scaling

18. BMayer@ChabotCollege.edu ENGR-43_Lec-05-3b_Thevein-Norton_Part-b.ppt 18 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Linearity cont.  Using Node Analysis For Resistive Circuits Yields Models Of The Form  The Model Can Be Made More Detailed Where –A and B are Matrices –s Is A Vector Of All Independent Sources  For Ckt Analysis Use The Linearity Assumption To Develop Special Analysis Methods Where –v Is A Vector Containing All The Node Voltages – f Is a Vector Containing Only independent Sources

19. BMayer@ChabotCollege.edu ENGR-43_Lec-05-3b_Thevein-Norton_Part-b.ppt 19 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Past Techniques  Case Study  Find V o  Redraw the Ckt to Reveal Special Cases After Untangling  Solution Techniques Available?      

20. BMayer@ChabotCollege.edu ENGR-43_Lec-05-3b_Thevein-Norton_Part-b.ppt 20 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Case Study cont.  Loop Analysis for V o  Node Analysis Out → Positive - -- -- --

21. BMayer@ChabotCollege.edu ENGR-43_Lec-05-3b_Thevein-Norton_Part-b.ppt 21 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Case Study cont.  Series-Parallel Resistor- Combinations  In other Words  By VOLTAGE Divider

22. BMayer@ChabotCollege.edu ENGR-43_Lec-05-3b_Thevein-Norton_Part-b.ppt 22 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Use Homogeneity Analysis  Find V o by Scaling  If V o is Given Then V 1 Can Be Found By The Inverse Voltage Divider  Now Use V S As a 2 nd Inverse Divider  Then Solve for V o  Assume That The Answer Is KNOWN How to Find The Input In A Very Easy Way ?

23. BMayer@ChabotCollege.edu ENGR-43_Lec-05-3b_Thevein-Norton_Part-b.ppt 23 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Homogeneity Analysis cont  The Procedure Can Be Made Entirely Algorithmic 1.Give to Vo Any Arbitrary Value (e.g., V’o = 1V ) 2.Compute The Resulting Source Value and Call It V’s 3.Use linearity 4.The given value of the source (Vs) corresponds to 5.Then The Desired Output

24. BMayer@ChabotCollege.edu ENGR-43_Lec-05-3b_Thevein-Norton_Part-b.ppt 24 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Homogeneity Comment  This is a Nice Tool For Special Problems  Normally Useful When There Is Only One Source Best Judgment Indicates That Solving The Problem BACKWARDS Is Actually Easier Than the Forward Solution-Path

25. BMayer@ChabotCollege.edu ENGR-43_Lec-05-3b_Thevein-Norton_Part-b.ppt 25 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Illustration  Homogeneity  Solve Using Homogeneity (Scaling)  Then By Ohm’s Law  Assume V’ out = V 2 = 1volt

26. BMayer@ChabotCollege.edu ENGR-43_Lec-05-3b_Thevein-Norton_Part-b.ppt 26 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Illustration  Homogeneity cont  Solve Using Homogeneity  Using Homogeneity Scale from Initial Assumption:  Again by Ohm’s Law  Then  Scaling Factor

27. BMayer@ChabotCollege.edu ENGR-43_Lec-05-3b_Thevein-Norton_Part-b.ppt 27 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Source Superposition  This Technique Is A Direct Application Of Linearity  Normally Useful When The Circuit Has Only A Few Sources

28. BMayer@ChabotCollege.edu ENGR-43_Lec-05-3b_Thevein-Norton_Part-b.ppt 28 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Illustration  Src Superposition  Consider a Circuit With Two Independent Sources: V S, I S  Calculated By Setting The CURRENT Source To ZERO (OPEN ckt) And Solving The Circuit  Calculated By Setting The VOLTAGE Source To ZERO (SHORT ckt) And Solving The Circuit  Now by Linearity

29. BMayer@ChabotCollege.edu ENGR-43_Lec-05-3b_Thevein-Norton_Part-b.ppt 29 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Illustration cont = +  Circuit With Current Source Set To Zero OPEN Ckt  Circuit with Voltage Source set to Zero SHORT Ckt  By Linearity

30. BMayer@ChabotCollege.edu ENGR-43_Lec-05-3b_Thevein-Norton_Part-b.ppt 30 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Illustration cont. = +  The Above Eqns Illustrate SUPERPOSITION  This approach will be useful if solving the two, 1-Src circuits is simpler, or more convenient, than solving a circuit with two sources  We can have any combination of sources. And we can partition any way we find convenient

31. BMayer@ChabotCollege.edu ENGR-43_Lec-05-3b_Thevein-Norton_Part-b.ppt 31 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Example  Solve for i 1 Loop equations Contribution of v1 Contribution of v2  Once we know the “partial circuits” we need to be able to solve them in an efficient manner = +  Alternative for i 1 (t) By SuperPosition: –Find i 1 ’’ by I-Divider

32. BMayer@ChabotCollege.edu ENGR-43_Lec-05-3b_Thevein-Norton_Part-b.ppt 32 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Numerical Example  Find V o By SuperPosition  Set to Zero The V-Src i.e., SHORT it Current division Ohm’s law Contribution by I src →

33. BMayer@ChabotCollege.edu ENGR-43_Lec-05-3b_Thevein-Norton_Part-b.ppt 33 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Numerical Example cont.  Find V o By SuperPosition  Set to Zero The I-Src i.e., OPEN it  Yields Voltage Divider (UN- tangle)  Finally, Add by SuperPosition  By V-Divider Contribution by V src

34. BMayer@ChabotCollege.edu ENGR-43_Lec-05-3b_Thevein-Norton_Part-b.ppt 34 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis WhiteBoard Work  Let’s Work this Nice Problem

35. BMayer@ChabotCollege.edu ENGR-43_Lec-05-3b_Thevein-Norton_Part-b.ppt 35 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Example  SuperPosition  Find V o Using Source SuperPosition  Set to Zero The I-Src i.e., OPEN it  Set to Zero The V-Src i.e., SHORT it

36. BMayer@ChabotCollege.edu ENGR-43_Lec-05-3b_Thevein-Norton_Part-b.ppt 36 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Example cont  Define V 1 on the V-Src ckt  If V 1 is known then V’o is obtained using the 6&2 Voltage-Divider V 1 can be obtained by series parallel reduction and divider

37. BMayer@ChabotCollege.edu ENGR-43_Lec-05-3b_Thevein-Norton_Part-b.ppt 37 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Numerical Example cont.2  Determine Current I 2 By Current Divider V”o Using Ohm’s Law  When in Doubt REDRAW  The Current Division  Finally The SuperPosition Addition

38. BMayer@ChabotCollege.edu ENGR-43_Lec-05-3b_Thevein-Norton_Part-b.ppt 38 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Sample Problem  Determine I o by Source SuperPosition  First Consider Only the Voltage Source Yields  Then  Second Consider Only the 3 mA I-Source Yields Current Divider

39. BMayer@ChabotCollege.edu ENGR-43_Lec-05-3b_Thevein-Norton_Part-b.ppt 39 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Sample Prob cont  Determine I o by Source SuperPosition  By I O2 Current Divider  Third Consider 4mA Src  The Current will Return on the Path of LEAST Resistance; Thus  So by Source Superposition

40. BMayer@ChabotCollege.edu ENGR-43_Lec-05-3b_Thevein-Norton_Part-b.ppt 40 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Illustration  Use Source Superposition to Determine I o  Open the Current Source  By Equivalent Resistance  Next Short the V-Source

41. BMayer@ChabotCollege.edu ENGR-43_Lec-05-3b_Thevein-Norton_Part-b.ppt 41 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Illustration cont  Looks Odd & Confusing → REDRAW  Finally By Linearity 1 1 2 2 3 3  Now Use I-Divider 2 2 2 2

42. BMayer@ChabotCollege.edu ENGR-43_Lec-05-3b_Thevein-Norton_Part-b.ppt 42 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis All Done for Today SuperPosition Of Plane-Polarized Light  Red & Green Light-Waves are Polarized in Perpendicular Planes Cyan = Red + Green

43. BMayer@ChabotCollege.edu ENGR-43_Lec-05-3b_Thevein-Norton_Part-b.ppt 43 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis

44. BMayer@ChabotCollege.edu ENGR-43_Lec-05-3b_Thevein-Norton_Part-b.ppt 44 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis

45. BMayer@ChabotCollege.edu ENGR-43_Lec-05-3b_Thevein-Norton_Part-b.ppt 45 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis

46. BMayer@ChabotCollege.edu ENGR-43_Lec-05-3b_Thevein-Norton_Part-b.ppt 46 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis

47. BMayer@ChabotCollege.edu ENGR-43_Lec-05-3b_Thevein-Norton_Part-b.ppt 47 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis

48. BMayer@ChabotCollege.edu ENGR-43_Lec-05-3b_Thevein-Norton_Part-b.ppt 48 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis

49. BMayer@ChabotCollege.edu ENGR-43_Lec-05-3b_Thevein-Norton_Part-b.ppt 49 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis

50. BMayer@ChabotCollege.edu ENGR-43_Lec-05-3b_Thevein-Norton_Part-b.ppt 50 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis

51. BMayer@ChabotCollege.edu ENGR-43_Lec-05-3b_Thevein-Norton_Part-b.ppt 51 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis