1. 8-bit Microprocessor Design
Prof. YoungChul Kim
Chonnam National University

2. Definition of Instruction Format and types
Op-code, Mnemonic-code and meaning of Instructions

3. Instruction Timing definition and meaning of stages
Instruction Timing Diagram
Type and meaning of timing stage according to instruction performing

4. Hardware definition for performing Instruction Fetch

5. Hardware definition for performing Instruction Decoding

6. Hardware definition for performing Instruction Execution

7. Define ALU functions for performing Instruction Execution
Definition of operation and meaning for ALU functional signal

8. Hardware definition for performing Store into Memory

9. Hardware definition for performing Write Back into Accumulator

10. Analysis on RTL Component
Analysis on hardware elements

11. VHDL Modeling of Combinational Logics(1)
2*1 MUX with 5-bit input
library IEEE; use IEEE.std_logic_1164.all;
entity MUX5 is
port ( A,B : in std_logic_vector(4 downto 0);
SEL : in std_logic;
Y : out std_logic_vector(4 downto 0));
end MUX5;
architecture RTL of MUX5 is
begin
process(A,B,SEL)
if SEL=’1’ then
Y <= A;
elsif SEL=’0’ then
Y <= B;
else
Y <= “-----“;
end if;
end process;
end RTL;
2*1 MUX with 8-bit input
library IEEE; use IEEE.std_logic_1164.all;
entity MUX8 is
port ( A,B : in std_logic_vector(7 downto 0);
SEL : in std_logic;
Y : out std_logic_vector(7 downto 0));
end MUX8;
architecture RTL of MUX8 is
begin
process(A,B,SEL)
if SEL=’1’ then
Y <= A;
elsif SEL=’0’ then
Y <= B;
else
Y <= “ “;
end if;
end process;
end RTL;

12. VHDL Model of Combinational Logics(2)
Incremeter
library IEEE; use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity INC is
port ( PC_ADDR : in
std_logic_vector(4 downto 0);
INC_ADDR : out
std_logic_vector(4 downto 0));
end INC;
architecture RTL of INC is
begin
INC_ADDR <= PC_ADDR + 1;
end RTL;
ALU
entity ALU is
port (OPCODE: in std_logic_vector(2 downto 0);
OP1,OP2 : in std_logic_vector(7 downto 0);
ZERO_FLAG : out std_logic;
ALU_OUT : out std_logic_vector(7 downto 0));
end ALU;
architecture RTL of ALU is
begin
process(OPCODE,OP1,OP2)
variable TMP: std_logic_vector(7 downto 0);
case OPCODE is
when “010” => TMP := OP1 + OP2;
when “011” => TMP := OP1 and OP2;
when “100” => TMP := OP1 xor OP2;
when “101” => TMP := OP2;
when others => TMP := OP1;
end case;
if TMP = 0 then
ZERO_FLAG <= ‘1’;
else
ZERO_FLAG <= ‘0’;
end if;
ALU_OUT <= TMP;
end process;
end RTL;

13. VHDL Modeling of Memory(1)
Program Data for verification

14. VHDL Modeling of Memory(2)
ROM
library IEEE; use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ROM is
port ( ROM_ADDR : in
std_logic_vector(4 downto 0);
ROM_DATA : out
std_logic_vector(7 downto 0));
end ROM;
architecture RTL of ROM is
subtype ROMWORD is std_logic_vector(7 downto 0);
type ROMTABLE is array(0 to 31) of ROMWORD;
constant ROM_TBL : ROMTABLE := ( “ ”,” ” );
begin
ROM_DATA <=
ROM_TBL(conv_integer(ROM_ADDR));
end RTL;
RAM
library IEEE; use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity RAM is
port (RAM_ADDR : in std_logic_vector(4 downto 0);
RAM_IN : in std_logic_vector(7 downto 0);
RAM_OUT : out std_logic_vector(7 downto 0);
MEM_RD, MEM_WR : in std_logic);
end RAM;
architecture RAM_A of RAM is
subtype WORD is std_logic_vector(7 downto 0);
type RAM is array(0 to 31) of WORD;
signal TMP: RAM := (….., " "," ",
" ", " ", " ",
" ", ” ", " ");
begin
process (MEM_RD, RAM_ADDR, RAM_IN) begin
if MEM_RD = '1' then
RAM_OUT <= TMP(conv_integer(RAM_ADDR));
elsif MEM_WR = '1' then
TMP(conv_integer(RAM_ADDR)) <= RAM_IN;
end if;
end process;
end RAM_A;

15. VHDL Modeling of Sequential Logics(1)
Symbol definition of Flip-Flop and Register
1-Bit Flip-Flop
library IEEE; use IEEE.std_logic_1164.all;
entity REG1 is
port ( CLK,RST,D,EN : in std_logic;
Q : out std_logic);
end REG1;
architecture RTL of REG1 is
begin
process(CLK,RST)
if RST = '0' then
Q <= '0';
elsif EN = '1' then
if CLK = '0' and CLK'event then
Q <= D;
end if;
end process;
end RTL;

16. VHDL Modeling of Sequential Logics(2)
5-Bit Register
library IEEE; use IEEE.std_logic_1164.all;
entity REG5 is
port ( CLK,RST,EN : in std_logic;
D : in std_logic_vector(4 downto 0);
Q : out std_logic_vector(4 downto 0));
end REG1;
architecture RTL of REG5 is
begin
process(CLK,RST)
if RST = '0' then
Q <= (others=>’0’);
elsif EN = '1' then
if CLK = '0' and CLK'event then
Q <= D;
end if;
end process;
end RTL;
8-Bit Register
library IEEE; use IEEE.std_logic_1164.all;
entity REG8 is
port ( CLK,RST,EN : in std_logic;
D : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0));
end REG8;
architecture RTL of REG8 is
begin
process(CLK,RST)
if RST = '0' then
Q <= (others=>’0’);
elsif EN = '1' then
if CLK = '0' and CLK'event then
Q <= D;
end if;
end process;
end RTL;

17. VHDL Modeling of Sequential Logics(3)
One-Hot Code signal generation for instruction timing stage

18. FSM for generating One-Hot Code
library IEEE; use IEEE.std_logic_1164.all;
entity CLK_GEN is
port( CLK,RST : in std_logic;
CLK_HOT : out
std_logic_vector(4 downto 0));
end CLK_GEN;
architecture CLK_GEN_A of CLK_GEN is
signal CURRENT_STATE,NEXT_STATE :
std_logic_vector(4 downto 0);
begin
process(CLK,RST)
if RST = '0' then
CURRENT_STATE <= "00000";
elsif CLK = '0' and CLK'event then
CURRENT_STATE <=
NEXT_STATE;
end if;
end process;
process(CURRENT_STATE)
begin
if CURRENT_STATE = "00000" then
NEXT_STATE <= "00001";
elsif CURRENT_STATE = "00001" then
NEXT_STATE <= "00010";
elsif CURRENT_STATE = "00010" then
NEXT_STATE <= "00100";
elsif CURRENT_STATE = "00100" then
NEXT_STATE <= "01000";
elsif CURRENT_STATE = "01000" then
NEXT_STATE <= "10000";
elsif CURRENT_STATE = "10000" then
else
end if;
end process;
CLK_HOT <= CURRENT_STATE;
end CLK_GEN_A;

19. Definition of Control Signals for each instruction Stage

20. Timing definition of control signal generation for each instruction
명령어와 제어 신호 발생 위치 정의

21. VHDL Modeling of a Control Signal Generator(1)
library IEEE; use IEEE.std_logic_1164.all;
package CONTROL_P is
constant S4 : std_logic_vector(4 downto 0) := "10000";
constant S3 : std_logic_vector(4 downto 0) := "01000";
constant S2 : std_logic_vector(4 downto 0) := "00100";
constant S1 : std_logic_vector(4 downto 0) := "00010";
constant S0 : std_logic_vector(4 downto 0) := "00001";
end CONTROL_P; --
use work.CONTROL_P.all;
entity CONTROL is
PORT( OP_D : in std_logic_vector(2 downto 0);
CLK_HOT : in std_logic_vector(4 downto 0);
ZERO_D : in std_logic;
CLK_D : in std_logic;
ACC_EN_D : out std_logic;
ALU_REG_EN_D : out std_logic;
MEM_RD_D : out std_logic;
MEM_WR_D : out std_logic;
PC_EN_D : out std_logic;
IR_EN_D : out std_logic;
MEM_REG_EN_D : out std_logic;
ZERO_EN : out std_logic;
MUX5_SEL : out std_logic;
MUX8_SEL : out std_logic);
end CONTROL;
architecture CONTROL_A of CONTROL is
signal ACC_EN_S,PC_EN_S : std_logic;
signal IR_EN_S,ALU_REG_EN_S : std_logic;
signal MEM_WR_S,MEM_REG_EN_S : std_logic;
signal ZERO_EN_S : std_logic;
signal MUX5_SEL_S,MUX8_SEL_S : std_logic;
begin
process(CLK_D)
if CLK_D = '1' and CLK_D'event then
ACC_EN_D <= ACC_EN_S;
PC_EN_D <= PC_EN_S;
IR_EN_D <= IR_EN_S;
ALU_REG_EN_D <= ALU_REG_EN_S;
MEM_WR_D <= MEM_WR_S;
MEM_REG_EN_D <= MEM_REG_EN_S;
ZERO_EN <= ZERO_EN_S;
MUX5_SEL <= MUX5_SEL_S;
MUX8_SEL <= MUX8_SEL_S;
end if;
end process;

22. VHDL Modeling of a Control Signal Generator(2)
process(CLK_HOT,OP_D,ZERO_D)
variable OP_D_COND : std_logic;
begin
if OP_D="010" or OP_D="011" OR
OP_D="100" then
OP_D_COND := '1';
else
OP_D_COND := '0';
end if;
case CLK_HOT is
when S0 =>
ACC_EN_S <= '0';
PC_EN_S <= '0';
MEM_WR_S <= '0';
MEM_RD_D <= '0';
IR_EN_S <= '1';
MUX5_SEL_S <= '1';
MUX8_SEL_S <= '1';
MEM_REG_EN_S <= '0';
ALU_REG_EN_S <= '0';
ZERO_EN_S <= '0';
when S1 =>
ACC_EN_S <= '0';
PC_EN_S <= '0';
MEM_WR_S <= '0';
IR_EN_S <= '0';
MUX5_SEL_S <= '1';
if OP_D_COND = '1' or OP_D = "101" then
MEM_REG_EN_S <= '1';
MEM_RD_D <= '1';
else
MEM_REG_EN_S <= '0';
MEM_RD_D <= '0';
end if;
MUX8_SEL_S <= '0';
MUX8_SEL_S <= '1';
ALU_REG_EN_S <= '0';
ZERO_EN_S <= '0';

23. VHDL Modeling of a Control Signal Generator(3)
when S2 =>
if OP_D = "000" then
PC_EN_S <= '0';
else
PC_EN_S <= '1';
end if;
ACC_EN_S <= '0'; MEM_WR_S <= '0';
IR_EN_S <= '0'; MUX5_SEL_S <= '1';
if OP_D_COND = '1' or OP_D = "101" then
MEM_RD_D <= '1';
MEM_RD_D <= '0';
if OP_D_COND = '1' then
ZERO_EN_S <= '1';
ZERO_EN_S <= '0';
MUX8_SEL_S <= '1'; MEM_REG_EN_S <= '0';
if (OP_D_COND = '1') or (OP_D = "101") or
(OP_D = "110") then
ALU_REG_EN_S <= '1';
ALU_REG_EN_S <= '0';
when S3 =>
if (OP_D = "001" and ZERO_D = '1') or
OP_D = "111" then
PC_EN_S <= '1';
else
PC_EN_S <= '0';
end if;
ACC_EN_S <= '0'; IR_EN_S <= '0';
if OP_D = "110" then
MEM_WR_S <= '1';
MEM_WR_S <= '0';
end if; if OP_D = "111" then
MUX5_SEL_S <= '0';
MUX5_SEL_S <= '1';
MUX8_SEL_S <= '1'; ALU_REG_EN_S <= '0';
if OP_D_COND = '1' or OP_D = "101" then
MEM_REG_EN_S <= '1';
MEM_REG_EN_S <= '0';
ZERO_EN_S <= '0'; MEM_RD_D <= '0';

24. VHDL Modeling of a Control Signal Generator(4)
when S4 =>
if OP_D_COND = '1' or OP_D = "101" then
ACC_EN_S <= '1';
else
ACC_EN_S <= '0';
end if;
MEM_WR_S <= '0';
IR_EN_S <= '0';
MUX5_SEL_S <= '1';
MUX8_SEL_S <= '1';
ALU_REG_EN_S <= '0';
MEM_RD_D <= '0';
MEM_REG_EN_S <= '0';
PC_EN_S <= '0';
ZERO_EN_S <= '0';
when others =>
ACC_EN_S <= '0';
PC_EN_S <= '0';
MEM_WR_S <= '0';
MEM_RD_D <= '0';
IR_EN_S <= '1';
MUX5_SEL_S <= '1';
MUX8_SEL_S <= '1';
MEM_REG_EN_S <= '0';
ALU_REG_EN_S <= '0';
ZERO_EN_S <= '0';
end case;
end process;
end CONTROL_A;

25. VHDL Modeling of a Top-Level Module of a Microprocessor
Entity
entity U_P is
port ( RESET,CLOCK : in std_logic);
end U_P;
Architecture
architecture U_P_A of U_P is
--component declaration
--signal declaration for intermediate storage
......…
--Define configuration of Components to use
begin
U0: MUX5 port map (PC_ADDR, IR_ADDR, MUX5_SEL, MUX5_OUT);
U1: MUX8 port map (ALU_OUT, RAM_OUT, MUX8_SEL, MEM_REG_IN);
U2: INC port map (PC_REG_OUT, PC_ADDR);
U3: REG1 port map (CLOCK, RESET, ZERO_IN, ZERO_EN, ZERO_OUT);
U4: REG5 port map (CLOCK, RESET, PC_EN, MUX5_OUT, PC_REG_OUT);
U5: REG8 port map (CLOCK, RESET, IR_EN, ROM_OUT, IR_OUT);
U6: REG8 port map CLOCK,RESET,ACC_EN ,ACC_IN,ACC_OUT);
U7: REG8 port map (CLOCK, RESET, ALU_REG_EN, ALU_IN, ALU_OUT);
U8: REG8 port map (CLOCK, RESET, MEM_REG_EN, MEM_REG_IN, ACC_IN);
U9: ALU port map (OPCODE, ACC_OUT, ACC_IN, ZERO_IN, ALU_IN);
U10: CONTROL port map (OPCODE, CLK_HOT, ZERO_OUT, CLOCK, ACC_EN, ALU_REG_IN, MEM_RD, MEM_WR, PC_EN, IR_EN, EM_REG_IN ZERO_EN, MUX5_SEL, MUX8_SEL);
U11: CLK_GEN port map (CLOCK, RESET, CLK_HOT);
U12: ROM port map (PC_REG_OUT, ROM_OUT);
U13: RAM port map (IR_ADDR, ALU_OUT, RAM_OUT, MEM_RD, MEM_WR);
end U_P_A;

26. Define Values for Verification and VHDL Test Bench
Values for verification on performing Program
Test Bench
library IEEE;
use IEEE.std_logic_1164.all;
entity TEST_BENCH is
end TEST_BENCH;
architecture TEST_BENCH_A of
TEST_BENCH is
component U_P
port (RESET,CLOCK : in std_logic);
end component;
signal RESET : std_logic :='0';
signal CLOCK : std_logic :='1';
for U0: U_P use entity work.U_P(U_P_A);
begin
U0 : U_P port map (RESET,CLOCK);
RESET <= '1' after 10 ns;
CLOCK <= not CLOCK after 5 ns;
end TEST_BENCH_A;
configuration TEST_BENCH_C of TEST_BENCH is
for TEST_BENCH_A
end for;
end TEST_BENCH_C;

27. Simulation Results and Waveform