1. P. Aspell PACE 3 design meeting 10,11/10/02 Thursday Analog : Morning : DELTA : Delta architecture, project status..... Paul Front-end design......... Michel Bandgap ref, DACs, Calibration circuit and procedure.......... Paul Organisation of remaining work........ Paul Afternoon : PACE_AM PACE_AM architecture, project status..... Paul Memory cell, Readamplifiers and Multiplexer...... Wojciech Memory cell reference.... Discussion ADC status and summary (Paul) and readout amplifier studies..... from Wojciech & Michel Organisation of remaining work,........ Paul Friday Digital : Morning through to afternoon: PACE 3 digital specification document....... Paul I2C status and sequencer status..... RAL High level system (PACE + ADC + K-chip) simulation........ Kostas Organisation of remaining work........... Paul

2. P. Aspell PACE3 prototyping and production schedule The Preshower schedule : Last year for prototyping …. 2003 Production starts in 2004 Installation in early 2006 All runs include Delta, PACE3AM and the K-chip MPW1 in 12/02 (looks like this will be March 2003) MPW2 in 6/03 Eng run 12/03 Production in 6/04 This is optimistic since it allows only 3 months for complete testing, design fix and resubmission yet it is still too late for the Preshower. One possibility is to replace MPW2 by Eng run 1 and hope.

3. P. Aspell Delta status DoneStill to do Preamp + Shaper ….Michel sch, sim, layout ext. sim., sim with PACEAM, verilog Linearity problems when using a transistor in the feedback of the shaper. Design done using reduced gain at the shaper followed by two inverting amp.s Move of IBM production to Burlington in the US means high ohmic res. now available. Also possible to use low value resistor with narrow width, variation less than high ohmic res. Bandgap sch, sim, layout, tested ext. sim., verilog DACs sch, sim, layout, tested ext sim., verilog DAC block sch, layout ….Danielle CalUnit sch, layout, sim from ext, verilog DACoSelect sch layout, sim I2C + reg.s - Verilog, synth, checking (high level code this week) Assembly sch, layout, sim

4. P. Aspell PACE3 Calibration 50400 0 1.53.1 Output Voltage (V) Signal (MIPs) LGHG Calibration of system with real single MIPs. Cal pulse… 1 to 50 MIPs Overlap between the two gains to inter-calibrate. Calibration procedure High Precision (HP) Range …. –43 mV to 37 mV, lsb = 0.312 mV (Range …. –12 to 10.6 MIPs, lsb = 1/11 th MIP) Low Precision (LP) Range …. –256 mV to 1.51 V, lsb = 6.9mV (Range …. –73 to 431 MIPs, lsb ~2 MIP) Will need to measure LP and HP response periodically to calibrate the calibration circuit. 256 0 Capacitor ~ 1.143pF ~ 431 MIPs equivalent 3.4 Calibration Circuit O/P Voltage Step DAC CalV input value LP HP Match the response of a real MIP with electronic injection pulse 3.5 mV step = 1 MIP Step response from the calibration circuit Overlap between the two gains HP, HG LP, LG (range > 400 MIPs) HP, LG (range to 10 MIPs) LP, HG (range to 50 MIPs)

5. P. Aspell PACEAM status DoneStill to do Notes Memory cell….Wojciech sch, sim, layout verilog(decoupling of ref) ReadAmps sch, sim, layout, ext. sim., verilog(single ended) Mux sch, sim, layout, ext. sim., verilog O/P buffersch, layout, sim., verilog (2 designs presented by M & W, 2 op-amp design simpler, needs checking with higher L). Memory referencesch, layout, sim., verilog (BG+DAC??+Opamp+ O/P pins) DAC block sch, layout ….Danielle DACoSelect sch,sim, layout, sim ContLogicfrom APVverilog (to be delivered this week) FIFO-Verilog, synth, checking (high level code this week) Seq-Verilog, synth, checking (high level code this week) I2C + reg.s - Verilog, synth, checking (high level code this week) DLL - Verilog, synth, checking (high level code this week) Assembly sch, layout, sim

6. P. Aspell PACE3 Power - Delta DeltaBudgetValues I have Preamp+Shaper 10mW/ch 2.7mW + 3mW = 5.7mW/ch DACs 8 x 4mW = 32mW 6 x 4mW = 24mW CalUnit 2.2mW 2.2mW DACoSelect 0 0 LVDS rec 1 x 7.2mW 1 x 7.2 mW I2C + reg.s 0 0 Total362mW 216mW

7. P. Aspell PACE3 Power - PACEAM BudgetValues I have now ReadAmps 4.2mW/ch 4mW/ch O/P buffer 0.8mW/ch ~22mW ?? DACs 8 x 4mW = 32mW 6 x 4mW = 24mW Digital part 53mW (APV measured) 53mW DACoSelect 0 0 LVDS rec 3 x 7.2mW = 22mW (sim) 22 mW LVDS tx 2 x 10.4mW = 21mW 21 mW I2C + reg.s 0 0 Total288mW 250mW Hence budget -> Delta (362) + PACEAM (288) = 650mW or ~20.3/ch Present Calculation -> Delta (216) + PACEAM (250) = 466mW or ~15mW/ch Absolute maximum for cooling system is 800mW/PACE3

8. P. Aspell Planning Analog : Complete front-end (M) and readout amplifiers (W) by next week (24/25-10-02) DAC block and Power-on reset (D) Simulation of analog channel from sch and extracted views (D) Verilog models of analog blocks, Memory ref, Memory drivers (W) Readout amplifier (M) DACoSelect circuits (P) Digital : Receive behavioral models of I2C, seq. and FIFO blocks from RAL before 18/10. Receive layout estimate of I2C, seq and FIFO ----------------- || ------------------------ Receive library containing APV cont.logic and DLL ------------------||---------------- Check behavioral models (K and P) Synthesis, ext. of parasitics, sim. Best/worse case etc. RAL Aim to complete the assembly by Xmas, extensive checking, sim. in Jan, Feb Submission estimate March 2003