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CPE 442 single-cycle datapath.1 Intro. To Computer Architecture CpE242 Computer Architecture and Engineering Designing a Single Cycle Datapath.

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Presentation on theme: "CPE 442 single-cycle datapath.1 Intro. To Computer Architecture CpE242 Computer Architecture and Engineering Designing a Single Cycle Datapath."— Presentation transcript:

1 CPE 442 single-cycle datapath.1 Intro. To Computer Architecture CpE242 Computer Architecture and Engineering Designing a Single Cycle Datapath

2 CPE 442 single-cycle datapath.2 Intro. To Computer Architecture Outline of Today’s Lecture °Recap and Introduction Where are we with respect to the BIG picture? (10 minutes) °The Steps of Designing a Processor (10 minutes) °Datapath and timing for Reg-Reg Operations (15 minutes) °Datapath for Logical Operations with Immediate (5 minutes) °Datapath for Load and Store Operations (10 minutes) °Datapath for Branch and Jump Operations (10 minutes)

3 CPE 442 single-cycle datapath.3 Intro. To Computer Architecture Course Overview Computer Design Instruction Set Deign ° Machine Language ° Compiler View ° "Computer Architecture" ° "Instruction Set Processor" "Building Architect" Computer Hardware Design ° Machine Implementation ° Logic Designer's View ° "Processor Architecture" ° "Computer Organization” “Construction Engineer”

4 CPE 442 single-cycle datapath.4 Intro. To Computer Architecture The Big Picture: Where are We Now? °The Five Classic Components of a Computer °Today’s Topic: Datapath Design Control Datapath Memory Processor Input Output

5 CPE 442 single-cycle datapath.5 Intro. To Computer Architecture The Big Picture: The Performance Perspective °Performance of a machine was determined by: Instruction count Clock cycle time Clock cycles per instruction °Processor design (datapath and control) will determine: Clock cycle time Clock cycles per instruction °In the next two lectures: Single cycle processor: -Advantage: One clock cycle per instruction -Disadvantage: long cycle time

6 CPE 442 single-cycle datapath.6 Intro. To Computer Architecture Recall the MIPS Instruction Set Architecture

7 CPE 442 single-cycle datapath.7 Intro. To Computer Architecture

8 CPE 442 single-cycle datapath.8 Intro. To Computer Architecture

9 CPE 442 single-cycle datapath.9 Intro. To Computer Architecture

10 CPE 442 single-cycle datapath.10 Intro. To Computer Architecture The MIPS Instruction Formats °All MIPS instructions are 32 bits long. The three instruction formats: R-type I-type J-type °The different fields are: op: operation of the instruction rs, rt, rd: the source and destination register specifiers shamt: shift amount funct: selects the variant of the operation in the “op” field address / immediate: address offset or immediate value target address: target address of the jump instruction optarget address 02631 6 bits26 bits oprsrtrdshamtfunct 061116212631 6 bits 5 bits oprsrt immediate 016212631 6 bits16 bits5 bits

11 CPE 442 single-cycle datapath.11 Intro. To Computer Architecture The MIPS Subset °ADD and subtract add rd, rs, rt sub rd, rs, rt °OR Immediate: ori rt, rs, imm16 °LOAD and STORE lw rt, rs, imm16 sw rt, rs, imm16 °BRANCH: beq rs, rt, imm16 °JUMP: j target optarget address 02631 6 bits26 bits oprsrtrdshamtfunct 061116212631 6 bits 5 bits oprsrtimmediate 016212631 6 bits16 bits5 bits

12 CPE 442 single-cycle datapath.12 Intro. To Computer Architecture An Abstract View of the Implementation Clk 5 RwRaRb 32 32-bit Registers Rd ALU Clk Data In DataOut Data Address Ideal Data Memory Instruction Instruction Address Ideal Instruction Memory Clk PC 5 Rs 5 Rt 16 Imm 32 Instruction Fetch Operand Fetch Execute

13 CPE 442 single-cycle datapath.13 Intro. To Computer Architecture Clocking Methodology °All storage elements are clocked by the same clock edge °Cycle Time = CLK-to-Q + Longest Delay Path + Setup + Clock Skew Clk Don’t Care SetupHold........................ SetupHold

14 CPE 442 single-cycle datapath.14 Intro. To Computer Architecture An Abstract View of the Critical Path °Register file and ideal memory: The CLK input is a factor ONLY during write operation During read operation, behave as combinational logic: -Address valid => Output valid after “access time.” Clk 5 RwRaRb 32 32-bit Registers Rd ALU Clk Data In DataOut Data Address Ideal Data Memory Instruction Instruction Address Ideal Instruction Memory Clk PC 5 Rs 5 Rt 16 Imm 32 Critical Path (Load Operation) = PC’s Clk-to-Q + Instruction Memory’s Access Time + Register File’s Access Time + ALU to Perform a 32-bit Add + Data Memory Access Time + Setup Time for Register File Write + Clock Skew

15 CPE 442 single-cycle datapath.15 Intro. To Computer Architecture Outline of Today’s Lecture °Recap and Introduction (5 minutes) Where are we with respect to the BIG picture? (10 minutes) °The Steps of Designing a Processor (10 minutes) °Datapath and timing for Reg-Reg Operations (15 minutes) °Datapath for Logical Operations with Immediate (5 minutes) °Datapath for Load and Store Operations (10 minutes) °Datapath for Branch and Jump Operations (10 minutes)

16 CPE 442 single-cycle datapath.16 Intro. To Computer Architecture The Steps of Designing a Processor 0) Instruction Set Architecture => Register Transfer Language Program Convert each instruction to RTL statements 1)Register Transfer Language program => Datapath Design Determine Datapath components Determine Datapath interconnects 2)Datapath components => Control signals 3)Control signals => Control logic => Control Unit Design

17 CPE 442 single-cycle datapath.17 Intro. To Computer Architecture Step: 0) Instruction Set Architecture => Register Transfer Language Program Register Transfer Language-RTL: The ADD Instruction °addrd, rs, rt mem[PC]Fetch the instruction from memory R[rd] <- R[rs] + R[rt]The ADD operation PC <- PC + 4Calculate the next instruction’s address

18 CPE 442 single-cycle datapath.18 Intro. To Computer Architecture RTL: The Load Instruction °lwrt, rs, imm16 mem[PC]Fetch the instruction from memory Addr <- R[rs] + SignExt(imm16) Calculate the memory address R[rt] <- Mem[Addr]Load the data into the register PC <- PC + 4Calculate the next instruction’s address

19 CPE 442 single-cycle datapath.19 Intro. To Computer Architecture Step 1) : RTL To Data Path Design – Data Path Components, °Adder °MUX °ALU 32 A B Sum Carry 32 A B Result Zero OP 32 A B Y Select Adder MUX ALU CarryIn Combinational Logic Elements

20 CPE 442 single-cycle datapath.20 Intro. To Computer Architecture Step 1) : RTL To Data Path Design – Data Path Components, Storage Elements: Register °Register Similar to the D Flip Flop except -N-bit input and output -Write Enable input Write Enable: -0: Data Out will not change -1: Data Out will become Data In Clk Data In Write Enable NN Data Out

21 CPE 442 single-cycle datapath.21 Intro. To Computer Architecture Step 1) : RTL To Data Path Design – Data Path Components, Storage Elements: Register File °Register File consists of 32 registers: Two 32-bit output busses: busA and busB One 32-bit input bus: busW °Register is selected by: RA selects the register to put on busA RB selects the register to put on busB RW selects the register to be written via busW when Write Enable is 1 °Clock input (CLK) The CLK input is a factor ONLY during write operation During read operation, behaves as a combinational logic block: RA or RB valid => busA or busB valid after “access time.” Clk busW Write Enable 32 busA 32 busB 555 RWRARB 32 32-bit Registers

22 CPE 442 single-cycle datapath.22 Intro. To Computer Architecture Step 1) : RTL To Data Path Design – Data Path Components, Storage Elements: Idealized Memory °Memory (idealized) One input bus: Data In One output bus: Data Out °Memory word is selected by: Address selects the word to put on Data Out Write Enable = 1: address selects the memory memory word to be written via the Data In bus °Clock input (CLK) The CLK input is a factor ONLY during write operation During read operation, behaves as a combinational logic block: -Address valid => Data Out valid after “access time.” Clk Data In Write Enable 32 DataOut Address

23 CPE 442 single-cycle datapath.23 Intro. To Computer Architecture Step 1) : RTL To Data Path Design – Data Path Components, Overview of the Instruction Fetch Unit °The common RTL operations Fetch the Instruction: mem[PC] Update the program counter: -Sequential Code: PC <- PC + 4 -Branch and Jump PC <- “something else” 32 Instruction Word Address Instruction Memory PC Clk Next Address Logic

24 CPE 442 single-cycle datapath.24 Intro. To Computer Architecture Outline of Today’s Lecture °Recap and Introduction Where are we with respect to the BIG picture? (10 minutes) °The Steps of Designing a Processor (10 minutes) °Datapath and timing for Reg-Reg Operations (5 minutes) °Datapath for Logical Operations with Immediate (5 minutes) °Datapath for Load and Store Operations (10 minutes) °Datapath for Branch and Jump Operations (10 minutes)

25 CPE 442 single-cycle datapath.25 Intro. To Computer Architecture Step 1): RTL To Data-Path Design Determine Data-path interconnects RTL: The ADD Instruction °addrd, rs, rt mem[PC]Fetch the instruction from memory R[rd] <- R[rs] + R[rt]The actual operation PC <- PC + 4Calculate the next instruction’s address oprsrtrdshamtfunct 061116212631 6 bits 5 bits

26 CPE 442 single-cycle datapath.26 Intro. To Computer Architecture RTL: The Subtract Instruction °subrd, rs, rt mem[PC]Fetch the instruction from memory R[rd] <- R[rs] - R[rt]The actual operation PC <- PC + 4Calculate the next instruction’s address oprsrtrdshamtfunct 061116212631 6 bits 5 bits

27 CPE 442 single-cycle datapath.27 Intro. To Computer Architecture RTL To Data Path Design – Data-path for Register-Register Operations °R[rd] <- R[rs] op R[rt] Example: add rd, rs, rt Ra, Rb, and Rw comes from instruction’s rs, rt, and rd fields ALUctr and RegWr: control logic after decoding the instruction 32 Result ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers RsRtRd ALU oprsrtrdshamtfunct 061116212631 6 bits 5 bits

28 CPE 442 single-cycle datapath.28 Intro. To Computer Architecture Register-Register Timing 32 Result ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers RsRtRd ALU Clk PC Rs, Rt, Rd, Op, Func Clk-to-Q ALUctr Instruction Memory Access Time Old ValueNew Value RegWrOld ValueNew Value Delay through Control Logic busA, B Register File Access Time Old ValueNew Value busW ALU Delay Old ValueNew Value Old ValueNew Value Old Value Register Write Occurs Here

29 CPE 442 single-cycle datapath.29 Intro. To Computer Architecture Outline of Today’s Lecture °Recap and Introduction Where are we with respect to the BIG picture? (50 minutes) °The Steps of Designing a Processor (10 minutes) °Datapath and timing for Reg-Reg Operations (15 minutes) °Datapath for Logical Operations with Immediate (5 minutes) °Datapath for Load and Store Operations (10 minutes) °Datapath for Branch and Jump Operations (10 minutes)

30 CPE 442 single-cycle datapath.30 Intro. To Computer Architecture RTL: The OR Immediate Instruction °orirt, rs, imm16 mem[PC]Fetch the instruction from memory R[rt] <- R[rs] or ZeroExt(imm16) The OR operation PC <- PC + 4Calculate the next instruction’s address immediate 0161531 16 bits 0 0 0 0 0 0 0 0 oprsrtimmediate 016212631 6 bits16 bits5 bits

31 CPE 442 single-cycle datapath.31 Intro. To Computer Architecture Datapath for Logical Operations with Immediate °R[rt] <- R[rs] op ZeroExt[imm16]] Example: ori rt, rs, imm16 32 Result ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt Don’t Care (Rt) Rd RegDst ZeroExt Mux 32 16 imm16 ALUSrc ALU 11 oprsrtimmediate 016212631 6 bits16 bits5 bits rd

32 CPE 442 single-cycle datapath.32 Intro. To Computer Architecture Outline of Today’s Lecture °Recap and Introduction Where are we with respect to the BIG picture? (50 minutes) °The Steps of Designing a Processor (10 minutes) °Datapath and timing for Reg-Reg Operations (15 minutes) °Datapath for Logical Operations with Immediate (5 minutes) °Datapath for Load and Store Operations (10 minutes) °Datapath for Branch and Jump Operations (10 minutes) °Assignment #3

33 CPE 442 single-cycle datapath.33 Intro. To Computer Architecture RTL: The Load Instruction °lwrt, rs, imm16 mem[PC]Fetch the instruction from memory Addr <- R[rs] + SignExt(imm16) Calculate the memory address R[rt] <- Mem[Addr]Load the data into the register PC <- PC + 4Calculate the next instruction’s address immediate 0161531 16 bits 0 0 0 0 0 0 0 0 0 0161531 immediate 16 bits 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 oprsrtimmediate 016212631 6 bits16 bits5 bits SignExt operation

34 CPE 442 single-cycle datapath.34 Intro. To Computer Architecture Datapath for Load Operations °R[rt] <- Mem[R[rs] + SignExt[imm16]]Example: lw rt, rs, imm16 11 oprsrtimmediate 016212631 6 bits16 bits5 bits rd 32 ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt Don’t Care (Rt) Rd RegDst Extender Mux 32 16 imm16 ALUSrc ExtOp Mux MemtoReg Clk Data In WrEn 32 Adr Data Memory 32 ALU MemWr

35 CPE 442 single-cycle datapath.35 Intro. To Computer Architecture RTL: The Store Instruction °swrt, rs, imm16 mem[PC]Fetch the instruction from memory Addr <- R[rs] + SignExt(imm16) Calculate the memory address Mem[Addr] <- R[rt]Store the register into memory PC <- PC + 4Calculate the next instruction’s address oprsrtimmediate 016212631 6 bits16 bits5 bits

36 CPE 442 single-cycle datapath.36 Intro. To Computer Architecture Datapath for Store Operations °Mem[R[rs] + SignExt[imm16] <- R[rt]] Example: sw rt, rs, imm16 32 ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt Rd RegDst Extender Mux 32 16 imm16 ALUSrc ExtOp Mux MemtoReg Clk Data In WrEn 32 Adr Data Memory 32 MemWr ALU oprsrtimmediate 016212631 6 bits16 bits5 bits

37 CPE 442 single-cycle datapath.37 Intro. To Computer Architecture Outline of Today’s Lecture °Recap and Introduction Where are we with respect to the BIG picture? (10 minutes) °The Steps of Designing a Processor (10 minutes) °Datapath and timing for Reg-Reg Operations (15 minutes) °Datapath for Logical Operations with Immediate (5 minutes) °Datapath for Load and Store Operations (10 minutes) °Datapath for Branch and Jump Operations (10 minutes)

38 CPE 442 single-cycle datapath.38 Intro. To Computer Architecture RTL: The Branch Instruction °beqrs, rt, imm16 mem[PC]Fetch the instruction from memory Cond <- R[rs] - R[rt]Calculate the branch condition if (COND eq 0)Calculate the next instruction’s address PC <- PC + 4 + ( SignExt(imm16) x 4 ) else PC <- PC + 4 oprsrtimmediate 016212631 6 bits16 bits5 bits

39 CPE 442 single-cycle datapath.39 Intro. To Computer Architecture Step 1) : RTL To Data Path Design – Data Path Components, Overview of the Instruction Fetch Unit °The common RTL operations Fetch the Instruction: mem[PC] Update the program counter: -Sequential Code: PC <- PC + 4 -Branch and Jump PC <- “something else” 32 Instruction Word Address Instruction Memory PC Clk Next Address Logic

40 CPE 442 single-cycle datapath.40 Intro. To Computer Architecture Datapath for Branch Operations °beq rs, rt, imm16We need to compare Rs and Rt! oprsrtimmediate 016212631 6 bits16 bits5 bits ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt Rd RegDst Extender Mux 32 16 imm16 ALUSrc ExtOp ALU PC Clk Next Address Logic 16 imm16 Branch To Instruction Memory Zero

41 CPE 442 single-cycle datapath.41 Intro. To Computer Architecture Binary Arithmetics for the Next Address °In theory, the PC is a 32-bit byte address into the instruction memory: Sequential operation: PC = PC + 4 Branch operation: PC = PC + 4 + SignExt[Imm16] * 4 °The magic number “4” always comes up because: The 32-bit PC is a byte address And all our instructions are 4 bytes (32 bits) long °In other words: The 2 LSBs of the 32-bit PC are always zeros There is no reason to have hardware to keep the 2 LSBs °In practice, we can simply the hardware by using a 30-bit PC : Sequential operation: PC = PC + 1 Branch operation: PC = PC + 1 + SignExt[Imm16] In either case: Instruction Memory Address = PC concat “00”

42 CPE 442 single-cycle datapath.42 Intro. To Computer Architecture Next Address Logic: Expensive and Fast Solution °Using a 30-bit PC: Sequential operation: PC = PC + 1 Branch operation: PC = PC + 1 + SignExt[Imm16] In either case: Instruction Memory Address = PC concat “00” 30 SignExt 30 16 imm16 Mux 0 1 Adder “1” PC Clk Adder 30 Branch Zero Addr Instruction Memory Addr “00” 32 Instruction 30

43 CPE 442 single-cycle datapath.43 Intro. To Computer Architecture Next Address Logic: Cheap and Slow Solution °Why is this slow? Cannot start the address add until Zero (output of ALU) is valid °Does it matter that this is slow in the overall scheme of things? Probably not here. Critical path is the load operation. 30 SignExt 30 16 imm16 Mux 0 1 Adder “0” PC Clk 30 BranchZero Addr Instruction Memory Addr “00” 32 Instruction 30 “1” Carry In Instruction

44 CPE 442 single-cycle datapath.44 Intro. To Computer Architecture RTL: The Jump Instruction °jtarget mem[PC]Fetch the instruction from memory PC concat target Calculate the next instruction’s address optarget address 02631 6 bits26 bits

45 CPE 442 single-cycle datapath.45 Intro. To Computer Architecture Instruction Fetch Unit 30 SignExt 30 16 imm16 Mux 0 1 Adder “1” PC Clk Adder 30 Branch equal Zero “00” Addr Instruction Memory Addr 32 Mux 1 0 26 4 PC Target 30 °jtarget PC concat target Jump Instruction 30 Instruction

46 CPE 442 single-cycle datapath.46 Intro. To Computer Architecture Putting it All Together: A Single Cycle Datapath 32 ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt Rd RegDst Extender Mux 32 16 imm16 ALUSrc ExtOp Mux MemtoReg Clk Data In WrEn 32 Adr Data Memory 32 MemWr ALU Instruction Fetch Unit Clk Zero Instruction Jump Branch °We have everything except control signals (underline) 0 1 0 1 01 Imm16RdRsRt

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