1. ECE 366 -- Computer Architecture Lecture Notes # 6 Shantanu Dutt How to Add To & Use the Basic Processor Organization To Execute Different Instructions

2. Instruction: lw ri x(16-bit offset) [r1 <= MEM[PC+X] Determine Phases (each may take >= 1cc and may be further decomposed): –1. Instruction Fetch: Same for all instr. of the same size (32 bits here) –2. Decode & Incr. PC (same as before). Note that X is offset from new PC value –3. Compute the address (PC+x) of the data to be fetched Requirements & Options: (I) F.U.: (a) Adder: Use adders avail (which?) OR Put in a new adder. (b) Need a sign extender for X (16 to 32 bits) (II) Registers: A data address reg. to store PC+X (III) (a) Connections from PC & X to Adder; (b) Connection from MAR to mem. address bus

3. Instruction: lw ri x(16-bit offset) [r1 <= MEM[PC+X] Phases: –4. Fetch Data Requirements & Options: (I) F.U.: None (II) Registers: A data reg. (MDR) to load data on the memory data bus (III) (a) Connections from mem data bus to MDR –5. ri <== MDR Requirements & Options: (I) F.U.: None (II) Registers: None (III) (a) Connections from MDR to write port of reg. file

4. Instruction Processing: Phase 1 -- Fetch Instruction: lw ri x(16-bit offset) [r1 <= MEM[PC+x] Memory Interface (Addr. + Data Bus) IRPC C.U. FSM PC Upd. Data Memory Memory Interface (Buses + Regs) Register File ALU O/P Reg. 1 1 Instruction Memory Connect PC to Addr. Bus & Read Mem. Onto Data Bus Load IR when Instr. Avail [IR <= Data Bus] Status signals Source & dest reg addr [PC=>Addr Bus; Mem[PC] => Data Bus]

5. Instruction Processing: Phase 2 -- Decode & Incr. PC Memory Interface (Addr. Bus) IRPC C.U. FSM PC Upd. Data Memory Memory Interface (Buses + Regs) Register File ALU O/P Reg. 2 Instruction Memory 2 Start State for lw Decode State Load PC w/ o/p of Update H/W [PC <= PC Upd o/p] Instruction: lw ri x(16-bit offset) [r1 <= MEM[PC+x]

6. Adding extra hardware for “lw”: MAR & MDR Instruction: lw ri x(16-bit offset) [ri <= MEM[PC+x] C.U. FSM +. Data Memory Memory Interface (Data Bus) Register File ALU O/P Reg. Status signals Memory Interface (Addr. + Data Bus) IR PC Instruction Memory Source & dest reg addr MDR MAR 4 MUX

7. Adding extra hardware for PC+X: Design 1 Design 1: Put in extra adder---(a) Expensive in logic and interconnects; (b) Time = 1cc (if + takes 1cc) C.U. FSM +. Data Memory Memory Interface (Data Bus) Register File ALU O/P Reg. Status signals Memory Interface (Addr. + Data Bus) IRPC Instruction Memory Source & dest reg addr MDR MAR 4 16->32 ext. 16 32 +. MUX

8. Instruction Processing: PC+X :Phase 3--Design 1 1cc operation (if + takes 1 cc) C.U. FSM +. Data Memory Memory Interface (Data Bus) Register File ALU O/P Reg. Status signals Memory Interface (Addr. + Data Bus) IRPC Instruction Memory Source & dest reg addr MDR MAR 4 16->32 ext. 16 32 +. MUX Load MAR

9. Adding extra hardware for PC+X: Design 2 Design 2: Use ALU adder---(a) Better but a little exp. in interconnects & MUXes; (b) Time = 3cc (if + takes 1cc) C.U. FSM +. Data Memory Memory Interface (Data Bus) Register File ALU O/P Reg. Status signals Memory Interface (Addr. + Data Bus) IRPC Instruction Memory Source & dest reg addr MDR MAR 4 16->32 ext. 16 32. MUX

10. Instruction Processing: PC+X :Phase 3(a)--Design 2 3cc entire operation: Phase 3(a) Load offset and PC in ALU reg (1cc) C.U. FSM +. Data Memory Memory Interface (Data Bus) Register File ALU O/P Reg. Status signals Memory Interface (Addr. + Data Bus) IRPC Instruction Memory Source & dest reg addr MDR MAR 4 16->32 ext. 16 32. MUX Select offset, PC Load ALU regs

11. Instruction Processing: PC+X :Phase 3(b)--Design 2 3cc entire operation: Phase 3(b) ADD in ALU, Load o/p reg. (1cc if + is 1cc) C.U. FSM +. Data Memory Memory Interface (Data Bus) Register File ALU O/P Reg. Status signals Memory Interface (Addr. + Data Bus) IRPC Instruction Memory Source & dest reg addr MDR MAR 4 16->32 ext. 16 32. MUX +. +. Select Add Load o/p reg.

12. Instruction Processing: PC+X :Phase 3(c)--Design 2 3cc entire operation: Phase 3(c) MAR <= o/p reg. C.U. FSM +. Data Memory Memory Interface (Data Bus) Register File ALU O/P Reg. Status signals Memory Interface (Addr. + Data Bus) IRPC Instruction Memory Source & dest reg addr MDR MAR 4 16->32 ext. 16 32. MUX Load MAR

13. Adding extra hardware for PC+X: Design 3 Design 3: Use PC adder---(a) Slightly less expensive than opt. 2; (b) Time = 1cc (if + takes 1cc) C.U. FSM +. Data Memory Memory Interface (Data Bus) Register File ALU O/P Reg. Status signals Memory Interface (Addr. + Data Bus) IRPC Instruction Memory Source & dest reg addr MDR MAR 4 16->32 ext. 16 32 MUX

14. Instruction Processing: PC+X :Phase 3--Design 3 1cc operation (if + takes 1cc) C.U. FSM +. Data Memory Memory Interface (Data Bus) Register File ALU O/P Reg. Status signals Memory Interface (Addr. + Data Bus) IRPC Instruction Memory Source & dest reg addr MDR MAR 4 16->32 ext. 16 32 MUX Read offset Load MAR

15. Adding extra hardware for PC+X: Design 4 Design 4: Use PC adder & Write Bus interconnection---(a) Least exp. & most general (applicable to other instr); (b) Time is slowest: 5cc for a 1 write port reg. file C.U. FSM +. Data Memory Memory Interface (Data Bus) Register File ALU O/P Reg. Status signals Memory Interface (Addr. + Data Bus) IRPC Instruction Memory Source & dest reg addr MDR MAR 4 16->32 ext. 16 32 Write Bus

16. Instruction Processing: PC+X :Phase 3(a)--Design 4 5 cc entire operation: Phase 3(a): Load scratchpad reg0 (sr0) from PC -- 1cc C.U. FSM +. Data Memory Memory Interface (Data Bus) Register File ALU O/P Reg. Status signals Memory Interface (Addr. + Data Bus) IRPC Instruction Memory Source & dest reg addr MDR MAR 4 16->32 ext. 16 32 Write Bus Load sr0 [sr0<=WB] Read PC [WB <=PC]

17. Instruction Processing: PC+X :Phase 3(b)--Design 4 5 cc entire operation: Phase 3(b): Load scratchpad reg1 (sr1) from offset-- 1cc C.U. FSM +. Data Memory Memory Interface (Data Bus) Register File ALU O/P Reg. Status signals Memory Interface (Addr. + Data Bus) IRPC Instruction Memory Source & dest reg addr MDR MAR 4 16->32 ext. 16 32 Write Bus Load sr1 [sr1<=WB] Read offset [WB<=offset]

18. Instruction Processing: PC+X :Phase 3(c)--Design 4 5 cc entire operation: Phase 3(c): Read sr0 and sr1 and load ALU I/p regs (1cc) C.U. FSM +. Data Memory Memory Interface (Data Bus) Register File ALU O/P Reg. Status signals Memory Interface (Addr. + Data Bus) IRPC Instruction Memory Source & dest reg addr MDR MAR 4 16->32 ext. 16 32 Write Bus Load ALU regs Read sr0 & sr1

19. Instruction Processing: PC+X :Phase 3(d)--Design 4 5 cc entire operation: Phase 3(d): ADD and load o/p reg. C.U. FSM +. Data Memory Memory Interface (Data Bus) Register File ALU O/P Reg. Status signals Memory Interface (Addr. + Data Bus) IRPC Instruction Memory Source & dest reg addr MDR MAR 4 16->32 ext. 16 32 Write Bus Select Add Load o/p reg. +

20. Instruction Processing: PC+X :Phase 3(e)--Design 4 5 cc entire operation: Phase 3(d): Read o/p reg. to WB, load MAR --1cc C.U. FSM +. Data Memory Memory Interface (Data Bus) Register File ALU O/P Reg. Status signals Memory Interface (Addr. + Data Bus) IRPC Instruction Memory Source & dest reg addr MDR MAR 4 16->32 ext. 16 32 Write Bus Load MAR [MAR <=WB] Read o/p reg. [WB <= o/p reg.]

21. Instruction Proc: Data Fetch in “lw”: Phase4 -- Design 4 >= 1cc operation (based on memory speed); will need to “wait” in this state until operation is completed C.U. FSM +. Data Memory Memory Interface (Addr + Data Bus) Register File ALU O/P Reg. Status signals Memory Interface (Addr. + Data Bus) IRPC Instruction Memory Source & dest reg addr MDR MAR 4 16->32 ext. 16 32 Write Bus Read mem Read MAR to Addr. Bus Load MDR when data available

22. Instr Proc: Performing ri <= MDR: Phase 5 -- Design 4 1cc operation C.U. FSM +. Data Memory Memory Interface (Data Bus) Register File ALU O/P Reg. Status signals Memory Interface (Addr. + Data Bus) IRPC Instruction Memory Source & dest reg addr MDR MAR 4 16->32 ext. 16 32 Write Bus Read MDR onto WB [WB <= MDR] Write to ri using dest. reg. addr. from IR

23. Some Control Unit FSM Design Tips The CU FSM is a Moore M/C; it is easier to reason about and design since instruction processing actions (i.e., control signals, which are the o/ps of the CU FSM) are associated w/ states The sequence [reg(s) read --> processing of resulting data --> reg(s) write] needs to be performed in a single state Different sequences of the above type need to be performed in different states if either: (a) there is a data dependency between them or (b) they need to share hardware resources (e.g., the internal write bus, the ALU adder) A particular sequence of the above type can take > 1 cc (e.g., instruction or data fetch from memory) in which case the CU generally needs to loop in a single state until a status signal (which is an i/p to the FSM) is received indicating completion of the operation

24. Some Control Unit FSM Design Tips (contd.) If in the sequence [reg(s) read --> processing of resulting data -- > reg(s) write] the destination reg(s) can be the same as the source reg(s) (reg(s) read) AND this sequence can take > 1 cc, then a race condition can occur, which can give a final incorrect result A race condition is one in which the o/p feeds back to the i/p before the operation is completed. This results in the i/p to the operation changing midway during the operation, thus resulting potentially in an incorrect o/p.