1. 241-440 @ W.S. 241-440 Computer System Design Lecture 4 Wannarat Suntiamorntut

2. 241-440 @ W.S. Part I : Single Data Path

3. 241-440 @ W.S. Outline Design a Processor step by step Requirement of instruction set Components and clocking Testing Datapath Control Datapath

4. 241-440 @ W.S. Five Component of Computer Datapath Control Processor MEMORYMEMORY Input Output

5. 241-440 @ W.S. Performance Perspective Performance of machine is determined by CPI Processor Design : clock cycle time clock per instruction Single cycle processor : adv. : one clock cycle per instruction disadv. : long cycle time

6. 241-440 @ W.S. Design Processor Step by Step 1. Analyze instruction set ==> Datapath requirement 2. Selection Set of datapath and establish clocking methodology 3. Assembly datapath meeting requirement 4. Analyze implementation of each instruction to determine setting of control 5. Assembly the control logic

7. 241-440 @ W.S. MIPS Instruction Format

8. 241-440 @ W.S. Step 1 ADDUrd, rs, rtSUBU rd, rs, rt ORI rt, rs, imm16

9. 241-440 @ W.S. Step 1 lw rt, rs,imm16 sw rt, rs, imm16 beq rs, rt, imm16

10. 241-440 @ W.S. RTL All instructions start by fetching Mem[PC] ADDU rd <= rs + rt;PC = PC + 4 SUBU rd <= rs + rt;PC = PC + 4 Ori rt <= rs + zero_ext(imm16);PC = PC + 4 LOAD rt <= mem[rs] + sign_ext(imm16); PC=PC + 4 STORE mem[rs] + sign_ext(imm16)<=rt; PC=PC+4 BEQ if rs = rt then PC=PC+sign_ext(imm16)||00 else PC = PC + 4

11. 241-440 @ W.S. Step 1 : The requirement from instruction Memory Data & Instruction Register (32 x 32) Read rsRead rt Write rt or rd PC Extender Add and sub register or extend immediate Add 4 or extended immediate to PC

12. 241-440 @ W.S. Step 2 : Components of datapath Combination Element Storage elements Clocking methodology

13. 241-440 @ W.S. Combination Elements AdderMUX

14. 241-440 @ W.S. Combination Elements ALU

15. 241-440 @ W.S. Storage Element : Register Similar to D-flip/flop Write enable negated(0) : Data out won’t change asserted(1) : Data out will be data in

16. 241-440 @ W.S. Register file Consist of 32 registers Ra select register to bus A Rb select register to bus B Rw select register to be written via bus W

17. 241-440 @ W.S. Storage : Ideal Memory One Input One Output Memory word is selected by Address, Write enable = 1 then the data will be written Clock input : is a factor only during write operation During read operation : behaves on combination logic.

18. 241-440 @ W.S. Clock Methodology

19. 241-440 @ W.S. Step 3 : Register Transfer Requirements --> Datapath Assembly Instruction Fetch Read Operands and Execute Operation

20. 241-440 @ W.S. Step 3 a : Instruction Fetch Unit Update PC : Sequence Code: PC <= PC + 4 Branch and Jump : PC <- something else

21. 241-440 @ W.S. Step 3b : Add & Sub

22. 241-440 @ W.S. Register-Register Timing

23. 241-440 @ W.S. Step 3c :Logical Operations with Immed.

24. 241-440 @ W.S. Step 3d: Load operations

25. 241-440 @ W.S. Step 3e : Store Operations

26. 241-440 @ W.S. Step 3f: Branch instruction beq rs, rt, imme16 mem[pc] equal <= rs = rt if (con eq 0) then PC<=PC+4+(signExt(imm16)x4); else PC <= PC + 4;

27. 241-440 @ W.S. Datapath for Branch Operations

28. 241-440 @ W.S. Put it all together

29. 241-440 @ W.S. Abstract view of critical path

30. 241-440 @ W.S. Step 4 : Control Path

31. 241-440 @ W.S. Meaning of control signal Rs, Rt and Imme16 hardwire to datapath nPC_sel : 0 => PC PC PC PC <= PC + 4 + signExt(Imm16) || 00

32. 241-440 @ W.S. Meaning of control signals ExtOp : Zero, signMemWr:write memory ALUsrc: 0=>regB, 1=>imme Memtoreg:1=>mem ALUcrt : add, sub, orReqWr : write dest. Reg.

33. 241-440 @ W.S. Control Signals

34. 241-440 @ W.S. Step 5 : Logic for each control signal

35. 241-440 @ W.S. Example : Load Flow

36. 241-440 @ W.S. Abstract View of implementation

37. 241-440 @ W.S. Next on Lecture 5