1. Final project design Simple CPU

2. NCKU EE CAD ASIC Lab 2 Jou, Jer Min, NCKU Instr. Memory i_datai_addr 32 PC operation Data Memory Register The basic flow for CPU 做資料的存取

3. NCKU EE CAD ASIC Lab 3 Jou, Jer Min, NCKU Instr. Memory i_datai_addr clk Data Memory d_dataout d_datain d_addr clk d_rw 32 When d_rw = 0 : read : d_dataout <= Mem[d_addr] When d_rw = 1 : write : Mem[d_addr]<=d_datain Always i_data <= Mem[i_addr] The Memory modules

4. NCKU EE CAD ASIC Lab 4 Jou, Jer Min, NCKU The hierarchy of our design i_addri_data Instruction Memory d_rwd_addr Data Memory d_dataind_dataout pcinstdmem_rw d_addr d_dataind_dataout FINAL 32 1 Design this block

5. NCKU EE CAD ASIC Lab 5 Jou, Jer Min, NCKU MIPS 指令格式

6. NCKU EE CAD ASIC Lab 6 Jou, Jer Min, NCKU Instruction Set Architecture (1/3)

7. NCKU EE CAD ASIC Lab 7 Jou, Jer Min, NCKU Instruction Set Architecture (2/3)

8. NCKU EE CAD ASIC Lab 8 Jou, Jer Min, NCKU Instruction Set Architecture (3/3) 類別指令例子意義說明 JJJ 25go to 25 無條件跳躍：跳到目的位址 JJALJAL 25go to 25 $ra = PC+1 無條件跳躍：用在程序呼叫 ，儲存返回位址 PC 0 1 2 3 :: addr Instr. Memory 32 bits Instr. 0 Instr. 1 Instr. 2 Instr. 3 PC = PC + 1 $ra = return address 這裡我們令 $R31 當 $ra 來使用

9. NCKU EE CAD ASIC Lab 9 Jou, Jer Min, NCKU MIPS 運算碼 格式指令 OpcodeFunction code RSLL6’b000000 RSRL6’b0000006’b000010 RSRA6’b0000006’b000011 RJR6’b0000006’b001000 RADD6’b0000006’b100000 RSUB6’b0000006’b100010 RAND6’b0000006’b100100 ROR6’b0000006’b100101 RXOR6’b0000006’b100110 RSLT6’b0000006’b101010 格式指令 Opcode IBEQ6’b000100 IBNE6’b000101 IADDI6’b001000 ISUBI6’b001001 ISLTI6’b001010 IANDI6’b001100 IORI6’b001101 ILW6’b100011 ISW6’b101011 JJ6’b000010 JJAL6’b000011

10. NCKU EE CAD ASIC Lab 10 Jou, Jer Min, NCKU 繳交資料  繳交日期： 6/30 p.m. 12:00 以前  繳交資料：  一份書面報告 (word 檔 )  簡易說明程式內容及執行結果。  組員工作分配。  程式檔案  Verilog 檔 檔名請命名成 ”groupXX.v”, XX 是組別號碼。 Top module 請命名成 FINAL 。  繳交方式：  與繳交 lab 作業方式相同，上傳至 ftp  其他：  若有 CPU 規格或上傳作業之問題，可寄信或到實驗室找助教

11. NCKU EE CAD ASIC Lab 11 Jou, Jer Min, NCKU  1 addi $r1,$r0,32---r1=r0+32  2 subi $r2,$r1,5----r2=r1-5  3 slti $r3,$r0,32---()r3=1  4 lw $r4,1($r0)-----r4=DMEM[1+0]  5 sw $r1,0($r0)-----DMEM[0+0]=r1  6 add $r5,$r1,$r2---r5=r1+r2  7 slt $r6,$r0,$r1---r6=1  8 sll $r7,$r1,1-----r7=r1<<1  9 j 13--------------pc=52  10 beq $r7,$r7,1-----pc=48  11 jr $r31-----------pc=60  12 bne $r1,$r0,-2----pc=44  13 addi $r8,$r0,8----r8=r0+8  14 jal 10-----------pc=40,r31=15*4  15 srl $r9,$r1,2-----r9=r1>>2  16 sra $r10,$r1,2----r10=r1>>2  17 sub $r11,$r1,$r2--r11=r1-r2  18 and $r12,$r2,$r4--r12=r2&r4  19 or $r13,$r2,$r4---r13=r2 | r4  20 xor $r14,$r2,$r4--r14=r2 ^ r4  21 andi $r15,$r2,22--r15=r2 & 22  22 ori $r16,$r2,22---r16=r2 | 22 Addr.dataAddr.data 00160 10170 20180 30190 40200 50210 60220 70230 80240 90250 100260 110270 120280 130290 140300 150310 32 27 1 DATA MEMORY ADDRdata 05 16 6 32 57 1 64 8 60 8 8 5 3 63 60 18 31

12. NCKU EE CAD ASIC Lab 12 Jou, Jer Min, NCKU  001000_00000_00001_00000_00000_100000  //addi $r1,$r0,32---r1=32  001001_00001_00010_00000_00000_000101  //subi $r2,$r1,5----r2=27  001010_00000_00011_00000_00000_100001  //slti $r3,$r0,32---r3=1  100011_00000_00100_00000_00000_000001  //lw $r4,1($r0)-----r4=DMEM[1]  101011_00000_00001_00000_00000_000000  //sw $r1,0($r0)-----DMEM[0]=r1  000000_00001_00010_00101_00000_100000  //add $r5,$r1,$r2---r5=r1+r2

13. NCKU EE CAD ASIC Lab 13 Jou, Jer Min, NCKU  000000_00000_00001_00110_00000_101010  //slt $r6,$r0,$r1---r6=1  000000_00001_00000_00111_00001_000000  //sll $r7,$r1,1-----r7=64  000010_00000_00000_00000_00000_001101  //j 13--------------pc=52  000100_01001_01001_00000_00000_000001  //beq $r7,$r7,1-----pc=48  000000_00000_00000_00000_00000_001000  //jr $r31-----------pc=60  000101_00000_00001_11111_11111_111110  //bne $r1,$r0,-2----pc=44

14. NCKU EE CAD ASIC Lab 14 Jou, Jer Min, NCKU  001000_00000_01000_00000_00000_001000  //addi $r8,$r0,8----r8=8  000011_00000_00000_00000_00000_001010  //jal 10------------pc=40,r31=60  000000_00001_00000_01001_00010_000010  //srl $r9,$r1,2-----r9=8  000000_00001_00000_01010_00010_000011  //sra $r10,$r1,2----r10=8  000000_00001_00010_01011_00010_100010  //sub $r11,$r1,$r2--r11=5  000000_00010_00100_01100_00000_100100  //and $r12,$r2,$r4--r12=3

15. NCKU EE CAD ASIC Lab 15 Jou, Jer Min, NCKU  000000_00010_00100_01101_00000_100101  //or $r13,$r2,$r4---r13=63  000000_00010_00100_01110_00000_100110  //xor $r14,$r2,$r4--r14=60  001100_00010_01111_00000_00000_010110  //andi $r15,$r2,22--r15=18  001101_00010_10000_00000_00000_010110  //ori $r16,$r2,22---r16=31