1. DEVICES AND COMMUNICATION BUSES FOR DEVICES NETWORK– PARALLEL BUS DEVICE PROTOCOLS 1

2.  ISA Bus (Industry Standard Architecture)  PCI Bus (Peripheral Component Interconnect)  ARM BUS 2

3. ISA Bus (Industry Standard Architecture)  It was first introduced by IBM PC to support its Intel 8088 microprocessor’s 8-bit.  Furth extended to 16 bits for the IBM Personal Computer/AT's Intel 80286 processor. The ISA bus was further extended for use with 32-bit processors as Extended Industry Standard Architecture (EISA).IBM Personal Computer/ATIntel 80286Extended Industry Standard Architecture 3

4. Five 16-bit and one 8-bit ISA slots on a motherboard16-bit8-bit 16-bit 4

5. 8-bit Data bus 5

6. 16-bit Data bus 6

7. ISA BUSES Bus width8 - bit Compatible with8 bit ISA Pins 62 Power+5 V, -5 V, +12 V, -12 V Clock4.7727266 MHz Bus width16 - bit Compatible with16 bit ISA Pins98 Power+5 V, -5 V, +12 V, -12 V Clock8.333333 MHz 8-bit ISA BUS 16-bit ISA BUS 7

8. ISA BUS  It is used with sound cards, disk drives or most network and video cards. 8-bit ISA(XT) CARD 16-bit ISA CARD 8

9. ISA BUS ISA Card 9

10. PINOUT of ISA BUS In the figure you can see the pinouts of the ISA BUS. The BUS is divided into two sides. The first side pins are named A1 to A31 and it is the components side. It consists of the address and data buses. The second side pins are named B1 to B31 and it is the solder side. This side contents the power pins and the signals related to interrupts and DMA transfers. 10

11. PINS DESCRIPTION OF ISA BUS  A0-A19 (pins A31 to A12): This twenty lines are the address BUS. They can address 1MB (2^20 bytes).  D0-D7 (pins A9 to A2): The data BUS consist of this eight data lines.  AEN (pin B11): It is used for the DMA controller to take over the data and address buses in a DMA transfer.  GND (pins B1, B10, B31): Connected to the ground of the computer.  +5V (pins B3, B29): 5V DC output of the power source.  -5V (pin B5): -5V DC output.  -12V (pin B7): -12V DC output.  +12V (pin B9): +12V DC output.  MEMW (pin B11): The µP asserts this signal when doing a write to the memory.  MEMR (pin B12): The µP asserts this signal when doing a read from the memory.  IOW (pin B13): The µP asserts this signal when doing a write to a port.  IOR (pin B14): The µP asserts this signal when doing a read from a port.  DACK0-DACK3 (pins B15, B17, B19 and B26): The DMA controller sets this signals to let a device know that the DMA has the control of the buses.  DRQ1-DRQ3 (pins B6, B16 and B18): Allow the peripheral boards to request the use of the buses.  +T/C (pin B27): The DMA controller sets this signal to let the peripheral know that the programmed number of bytes has been sent.  IRQ2-IRQ7 (pins B4, B21, B22, B23, B24 and B25): Interrupt signals. The peripheral devices sets this signals to request for the attention of the µP  ALE (pin 28): This signal is used for the µP to lock the 16 lower address BUS in a latch during a memory (or port) input/output operation.  CLOCK (pin 20): Is the system clock.  OSC (pin 30): Is a high frequency clock which can be used for the I/O boards. 11

12. Describing the Read operation of the ISA  CPU sends out a high on the ALE signal, then sends out the A0-A19 lines. On the address of the target port to be read will be latched.  Then the BUS takes the -IOR signal to a low level. So that the addressed device will take a data byte to the D0- D7 data bus.  The microprocessor will read then the data bus and take the -IOR signal to a high again. 12

13. Describing the Read/Write operation of the ISA  The only difference between a memory read/write cycle and a port read/write cycle is that in a memory cycle the -MEMR and -MEMW signals will be asserted, working the same way as -IOR and -IOW do. 13

14. Limitation of ISA 1.ISA Bus is slow, hard to use and bulky 2.ISA is not like a PnP(Plug-n-Play). 3.Limited number of interrupts. 4.Motherboard gets 32-bit data from ISA BUS at two times. Meanwhile at this time ISA BUS declares “wait state” to the motherboard. Therefore ISA BUS may reduce System Performance. 5.ISA cards are more cumbersome to install than other cards because I/O addresses, interrupts and clock speed must be set using jumpers and switches on the card itself. 14

15. PCI PARALLEL BUS PROTOCOL 15

16. PCI (Peripheral Component Interconnect )  PCI(Peripheral Component Interconnect) bus is based on ISA (Industry Standard Architecture) Bus.  Introduced by Intel in 1992.  PCI provides direct access to system memory.  This configuration allowed for higher performance without slowing down the processor  The PCI Bus was originally 33Mhz and then changed to 66Mhz.  PCI Bus became big with the release of Windows 95 with “Plug and Play” technology. 16

17. Image of PCI Slots 17

18. 32- Bit vs 64- Bit Slots/ Boards 18

19. PCI Pin-out Diagram 19

20. PCI Bus In Relation to System Bus The PCI adapter is a custom circuit with these main functions:  To act as a PCI bus target when a PCI bus master requests a read or write to memory.  To act as a PCI bus master when a CPU requests a PIO operation  To manage PCI bus arbitration, allocating bus use to devices as they request it.  To interface PCI interrupt signals to the system bus and the CPU 20

21. 21 PCI System Bus Performance What makes the PCI bus one of the fastest I/O bus used today?  Three features make this possible:  Burst Mode: allows multiple sets of data to be sent.  Full Bus Mastering: the ability of devices on the PCI bus to perform transfers directly.  High Bandwidth Options: allows for increased speed of the PCI.  PCI driver can access the hardware automatically as well as by the programmer assigned addresses.  Simplified addition and deletion (attachment and detachment) of the system peripherals.

22. 22 How PCI Compares to Other Buses Table 1: How PCI compares to other buses (Tyson, 2004a; Quatech, 2004c) Bus Type Bus Width Bus SpeedMB/secAdvantagesDisadvantages ISA16 bits8MHz16 MBpslow cost, compatibility, widely used low speed, Jumpers & DIP switches. becoming obsolete PCI64 bits133 MHz1 GBpsvery high speed, Plug & Play, dominant board- level bus incompatible with older systems, can cost more CompactPCI64 bits33MHz132 MBpsdesigned for industrial use, hot swapping/Plug & Play, ideal for embedded systems lower speed than PCI, need adapter for PC use, incompatible with older systems

23. 23 Plug and Play  Requirements for full implementation:  Plug and Play BIOS  Extended System Configuration Data (ESCD)  Plug and Play operating system  Tasks it automates:  Interrupt Requests (IRQ)  Direct Memory Access (DMA)  Memory Addresses  Input/Output (I/O) Configuration

24. 24 How PCI Works: Installing A New Device  Once a new device has been inserted into a PCI slot on the motherboard 1.Operating System Basic Input/Output System (BIOS) initiates Plug and Play (PnP) BIOS. 2.PnP BIOS scans the PCI bus for any new hardware connected to the bus. If new hardware is found, it will ask for identification. 3.The device will respond with its identification and send its device ID to the BIOS through the bus. 4.PnP checks the Extended System Configuration Data (ESCD) to make sure the configuration data already exists for the card. (If the card is new, then there will be no data for it.)

25. 25 New Device Cont… 5.PnP will assign an Interrupt Request Line, Direct Memory Access, memory address and Input/Output settings to the card, then stores the information in the ESCD. 6.When the Windows software loads, it will check the PCI bus and the ESCD to see if there is new hardware. Windows will alert the user that new hardware has been found if there is new hardware installed and will also identify the hardware. 7.Windows will determine the device and attempt to install its driver. The operating system may ask the user to insert a disk containing the driver or direct it to where the driver is located. In the event that Windows is unable to determine what the device is, it will provide a dialog window so the user can identify the hardware and load its driver.

26. 26 How a Device Works Example: PCI-based sound card 1.The sound card will convert the analog signal to a digital signal. 2.The digital audio data carried across the PCI bus to the bus controller, which determines which device on the PCI device has the priority to send data to the central processing unit (CPU) and whether the data will go directly to the CPU or to the system memory. 3.If the sound card is in recording mode, the bus controller will assign a high priority to the data coming from the sound card. It will send the sound cards data over the bus bridge to the system bus. 4.The system bus will save the data in system memory. When the recording is complete, then it will be up to the user to save the data from the sound card on either the hard drive, or will remain in memory for additional processing.

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28. PCI-X (PCI extended)  133 MBps to as much as 1 GBps  Backward compatible with existing PCI cards  Used in high bandwidth devices (Fiber Channel, and processors that are part of a cluster and Gigabit Ethernet)  Maximum 264 MBps throughput, uses 8, 16, 32, or 64 bit transfers 28

29. PCI bus Applications It connects  display monitor,  printer,  character devices,  network subsystems,  video card,(AGP Controller)  modem card,  hard disk controller, 29

30. ARM BUS Self study 30