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Published byMercy Chapman Modified over 9 years ago
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Practical Strategies for Power-Efficient Computing Technologies Karim Al-Sheraidah December 8 th 2011
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2 Overview Survey of Power reduction techniques ~8x improvement in power efficiency No performance lose Voltage Scaling Optimum VDD = 0.5 V IBM Blue Gene system
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3 Introduction The Regime of interest
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4 Introduction cont… P active = C eff V 2 ƒ + I leak V C eff is V dependent C eff V 2 ∞ V 2.5 ƒ is linearly V dependent ƒ = α(V – V 0 ) V 0 ≈ 0.25 V P active = αC eff V 2 (V – V 0 ) + I leak V ∞ V 3
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5 The Case for Voltage Scaling Departing from scaling theory
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6 The Case for Voltage Scaling Optimum VDD = 0.5 v
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7 The Case for Voltage Scaling cont… Optimum VDD = 0.5 v
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8 Enablement (1) Operating Margin improvement
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9 Enablement (2) Low variability devices ET-SOI Fin-FET
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10 Enablement (3) Digital Noise Resistive:dV R /V DD = IR/V DD ∞ ( V DD – V T ) 1.5 /V DD Capacitive:dV C /V DD = [C agg V DD /(C agg + C vic )]/V DD = C agg /(C agg + C vic ) Inductive:dV L /V DD = [ L ∂I/∂t ]/V DD ∞ (L I)/(V DD ҭ ) ∞ (V DD – V 0 )( V DD – V T ) 1.5 /V DD
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11 Enablement (4) On-Chip Power System
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12 Case study (IBM Blue Gene) - Top500 HPC from 2004 to 2007 - Operating at 850MHz - Performance of up to 13.9Tflop - 4096 parallel processor cores - Three chip voltage bins
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13 Conclusion - Power efficiency through voltage scaling. - Optimum V DD = 0.5 v. - lowering of variability. - Increasing margin. - Massive parallelism. - High integration.
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