1. Presented by: Reshef Schreiber Itay Leibovitz Instructed by: Eran Segev

2. Board Objectives The Serial Communication Board (SCB) enables the DSP developer to interface to the commercial DSP evaluation board using common serial channels: The Serial Communication Board (SCB) enables the DSP developer to interface to the commercial DSP evaluation board using common serial channels: RS 232 RS 232 USB USB McBSP channels McBSP channels The SCB expand the I/O capabilities of the evaluation board The SCB expand the I/O capabilities of the evaluation board The SCB interfaces mechanically and electrically to the External Memory Interface (EMIF) connectors of the evaluation board The SCB interfaces mechanically and electrically to the External Memory Interface (EMIF) connectors of the evaluation board

3. DSP Evaluation Board

4. SCB Interfaces SCB Channel A Channel B RS-232 USB Channel A Channel B McBSP External Memory Interface (EMIF) Power 3.3 V McBSP Signals Interrupts Channel A

5. Part List FPGA: FPGA: ALTERA FLEX10k: EPF10K30ATC 144-pin ALTERA FLEX10k: EPF10K30ATC 144-pin ALTERA EPC2 ALTERA EPC2 RS232: RS232: DUART: EXAR ST16C2552CJ44 DUART: EXAR ST16C2552CJ44 Transceivers: 2 MAXIM-IC MAX3241 Transceivers: 2 MAXIM-IC MAX3241 1.8432 MHz Crystal 1.8432 MHz Crystal 2 RS232 9-pin male connectors 2 RS232 9-pin male connectors USB: USB: 2 cypress SL811HS 2 cypress SL811HS 2 USB Connectors Type A 2 USB Connectors Type A 2 48MHz Crystals 2 48MHz Crystals

6. Implementation The DSP will approach the USB and RS232 according to specific external address. The DSP will approach the USB and RS232 according to specific external address. All signals (address, data, control) will go through the FPGA. All signals (address, data, control) will go through the FPGA. The FPGA will produce read/write cycles for each block, and handle interrupts. The FPGA will produce read/write cycles for each block, and handle interrupts.

7. SCB block diagram Evaluation Board Interface (FPGA) McBSP USB RS232 Channel A Channel B Channel A Local Bus External Memory Interface (EMIF) Interrupts Channel A

8. FPGA block diagram EMIF to Local Bridge Interrupt Controller Reset Function Reset Local BusEMIF DUART Reset USB1 Reset USB2 Reset DUART Interrupt 1 DUART Interrupt 2 USB1 Interrupt USB2 Interrupt Interrupt 1 Interrupt 2 Interrupt 3 Interrupt 4

9. RS - 232 DUART Bus Transceiver Bus Transceiver Local Bus

10. USB Interface Local Bus

11. Power Consumption The DSP can supply 1A to the daughtercard The DSP can supply 1A to the daughtercard The SCB power consumption: The SCB power consumption: USB: 25mA (Max) USB: 25mA (Max) DUART: 1.2mA (Max) DUART: 1.2mA (Max) MAX3241: 1mA (Max) MAX3241: 1mA (Max) ALTERA: 100mA (at 20MHz) ALTERA: 100mA (at 20MHz) Total: ~250mA (with 50% overhead) Total: ~250mA (with 50% overhead)

12. Schedule Next 2 weeks: Final schematics Next 2 weeks: Final schematics Till mid February: Editing card + VHDL Till mid February: Editing card + VHDL Start debugging Start debugging

13. Top Level Schematics

14. RS-232 Schematics

15. USB Schematics