CORE Generator System V3.1i

CORE Generator System V3.1i
CORE Generator System V3.1i IP Catalog and CORE Delivery System

Agenda Core Generator Overview Core Generator Overview
What’s New in 3.1i? Smart IP Technology Using the Core Generator Xilinx IP Center Design Reuse & the Core Generator Summary Core Generator Overview

Xilinx CORE Generator Go Farther, Faster
Features Benefits Complete IP Cataloging, Sorting, Selection and Delivery System Broad Range of Design Entry, Batch and Scriptable Flows Supported Enables Capture, Catalog and Delivery of Customer Developed IP Generation of HDL Instantiation Templates and Behavioral Models Internet Enabled Quickly access IP Generators, IP Data Sheets, and IP Provider Contact Info. Use Existing Design and Simulation Tools (no need to learn new design flow) Promotes Design Reuse; Capture of Design Knowledge; Recovery of Expensive IP Development Effort VHDL and Verilog Flows Supported Direct Web Links to IP Updates, IP Tools, and IP Providers The CORE Generator System allows centralized access to Cores, data sheets, parameter options for core customization, and help functions. The Xilinx CORE Generator System provides the user with a catalog of ready-made IP functions ranging in complexity from simple arithmetic operators such as adders, accumulators and multipliers, to system-level building blocks including filters, transforms and memories. The CORE Generator System can customize a generic functional building block such as a FIR filter or a multiplier to meet the needs of your application, and simultaneously delivers high levels of performance and area efficiency. This is accomplished by the use of Xilinx’s CORE-friendly FPGA architectures and by the application of Xilinx Smart-IP™ technology. The Core Generator enables Design Reuse. You can package and add your own IP to your local copy of the Core Generator Catalog. And the Core Generator works in conjunction with the Xilinx IP Center on the world wide web, to keep you up to date with the latest IP and software upgrades.

Xilinx CORE Generator IP Catalog & Core Delivery System
LogiCOREs Fully tested, documented and supported by Xilinx Utilize Smart-IP for predictable performance AllianceCOREs Sold and supported by Xilinx AllianceCORE partners All IP optimized for Xilinx (some use Smart-IP, typically supplied as EDIF “black box” netlist) Reference Designs Demonstrate a particular design, technique, or IP usage Customized or used as-is; Customer does final verification Reference Designs provided free, but unsupported Our Xilinx core development effort, LogiCORE was the first FPGA program and is the most successful program in the industry today. LogiCORE products are designed, sold, licensed and supported by Xilinx. Generic LogiCORE products, such as parameterizable DSP building blocks and memory cores, are included with the Xilinx CORE Generator software to licensed software customers. System level cores such as PCI, Reed Solomon are also available as optional products. The AllianceCORE program is a cooperative effort between Xilinx and third-party IP developers. Through this program, Xilinx has successfully produced an extremely broad selection of industry standard solutions for use with our programmable logic devices. To qualify for the program, cores must meet a set of criteria that ensure they are capable of delivering value and performance. All AllianceCORE products have been implemented and verified in a Xilinx device. Reference Designs that are in this program are functional designs examples that offer considerable development time savings to customers who are ready to ship new systems. These designs are modular, generic platforms that are appropriate for a wide variety of end user products.

LogiCORE Application Areas
Basic Elements Multiplexers and Parallel to Serial Converters Communications and Networking ADPCM, HDLC Controllers DSP and Video Image Processing From small building blocks (eg. Time Skew Buffers), to larger system level functions (eg.FIR Filters and Correlators) System Logic Accumulators, Adders, Subtracters, Complementers, Multipliers, Integrators and Square Root generator functions Pipelined Delay Elements, Single and Dual Port RAM, ROM, and Synchronous FIFOs Standard Bus Interfaces PCI Master and Slave Interfaces, PCI Bridge Here are the main categories of IP that Xilinx LogiCORE addresses and some examples in each group.

AllianceCORE Application Areas
Communications ATM Forward Error Correction Reed-Solomon Encoder/Decoder T1 Framers Processors Processor Peripherals Bus Interfaces PCMCIA USB DSP - Image Processing Xilinx seeks out AllianceCORE partners who can complement the Xilinx LogiCORE product offering. Where Xilinx does not offer a LogiCORE for a particular function, we partner with an AllianceCORE partner to offer that function. A large percentage of Xilinx AllianceCORE partners focus on Data and Tele-Communication or Processors and processor peripherals

Agenda Core Generator Overview What’s New in 3.1i? Smart IP Technology
Using the Core Generator Xilinx IP Center Design Reuse & the Core Generator Summary What’s New in 3.1i?

New and Improved in the CORE Generator 3.1i
Faster startup and IP generation New IP sorting and cataloging Organize IP by function, family, provider, alphabetical Improved functional simulation setup and flow Direct web links to IP Center, IP tools, IP providers Dynamic symbols during core parameterization These are the key features of the new 3.1i release of Xilinx Foundation Series and Alliance Series software that contains the CORE Generator feature. The initialization time of the CORE Generator has been improved and the elapsed time for IP generation has improved. This improves you overall design cycle. There are a vast array of cores included with the Core Generator. 3.1i features new sorting and cataloging capabilities that allow you to easily find the IP you need. HDL behavioral simulation flow has been improved. We now write out analyze order files for VHDL and Verilog that shows the order in which the behavioral models must be compiled . That file is updated with each IP Update. We provide simulation models pre-extracted in the Xilinx installation tree, so it is not necessary to run the get_models program. The Core Generator User Interface now has direct links to key Xilinx web support pages such as the Xilinx IP Center, Xilinx Technical Support and our partner IP providers. A new GUI feature called Dynamic Symbols displays a graphical representation of the pins that are affected dynamically as you adjust the parameters for each core. These representations are specific to each core.

Using the Core Generator Xilinx IP Center Design Reuse & the Core Generator Summary Smart IP Technology

Architecture Tailored to Cores
Segmented Routing Advantages Efficient Routing Predictable Timing Low Power Core1 Core2 Xilinx Segmented Routing Non-Segmented Routing Distributed Memory Advantages Portable RAM based Cores Improved Logic Efficiency by 16X High Performance Cores RAM available locally to the Core Note: This slide can be used as a back up to demonstrate the advantages of Xilinx cores based on Xilinx architectures. Also our cores demonstrate our architectural advantages very well. Xilinx FPGA architectures use segmented routing. Short metal line segments are used to interconnect the logic elements within a core without interfering with the interconnection needs of other cores. Hence we can turn the core into a single module. The device on the left is a Xilinx device with two core modules with clean and efficient routing internal to the routing. In the case of the non-segmented routing the core’s logic is not modular and hence the logic gets routed all over the chip, hence competing with routing resources and making the timing unpredictable. FPGAs without segmented routing have less control over where the logic for each core is placed, and the long metal lines that are required for one core may be needed to interconnect a second or third core. The net result is a loss in performance and predictability. Benchmarks show a 30% reduction in performance as more cores are added to FPGAs without segmented routing. You do not know how fast your design will run until it is completed. With Xilinx cores the performance is specified in a data sheet and is consistent independent how many cores are used. With distributed RAM each core has access to just the right amount of RAM within the core. The ability to distribute many small memories within each core yields several advantages. The performance can improve through shorter routing and the elimination of routing congestion caused by multiple busses connecting the RAM to the core. If a small FIFO is needed in one part of a design it can be implemented where it is used and it can be implemented with the exact bit-width, number of words, and control signals that are required by the design. No compromises need to be made. Design efficiency can also be improved. For example, in DSP applications, incoming data can be stored in distributed RAM instead of individual flip-flops yielding a 16-to-1 density improvement for the buffer and a 3-to-1 overall reduction in CLB count for the same filter.

Xilinx Smart-IP Technology Pre-defined Placement & Routing
Fixed Placement & Pre-defined Routing Guarantees Performance Guarantees I/O Fixed Placement I/Os Relative Placement Logic Predictability: Other Logic Has No Effect on the Core With relative placement of the logic within a core, you get logic predictability. Because the logic has consistent internal placement, the performance of a core remains constant regardless of its position in the device. This is the intelligent software part of Smart-IP technology. In addition to the modular routing capability, we can keep track of the relative location of a core’s logic. Hence, we can floorplan the core or fix its placement with respect to the I/O. For guaranteed performance we can even fix the placement and pre-define the routing. For example the Xilinx DSP cores use only relative placement, but for the more performance sensitive PCI design we use the Fixed Placement and Pre-defined routing strategy. Enhances Performance & Predictability

Xilinx Smart-IP Technology Delivers Design Predictability
80 MHZ 80 MHZ Performance Independent of: Core placement Number of Cores used in the device 80 MHZ 80 MHZ Performance Independent of: Device Size Designs can be migrated to larger devices without any performance degradation. Because of the use of regular local logic and interconnect as well as segmented routing, the IP Modules can be placed any where on the device which out impacting on performance. Because the IP Modules use regular local logic and interconnect, you can also place multiple copies of the same module on a device and they will ALL continue to function at the published performance speeds. For the same reasons you can also migrate an IP Module from smaller devices to larger devices without degrading the modules performance Without Xilinx Segmented Architecture . . . you may experience a 30% performance degradation

Using the Core Generator Xilinx IP Center Design Reuse & the Core Generator Summary Using the Core Generator

Xilinx Core Generator User Interface & Web Access
Here is an example of a user interaction with the Core Generator. First note the links to the Xilinx web support sites in the lower right hand corner These buttons immediately open a browser window to each site. Next lets click on the View Catalog option.This provides that capability to sort available cores by core function, alphabetically, by vendor,or by Xilinx silicon family. In this example we have selected to sort by Function (the default). In this example we have drilled down from Communications and Networking to Telecommunications and listed all of the telecommunications cores. Then we selected a Reed Solomon core (on the right). Double clicking on the core name brings up a contact sheet… and also a core overview paragraph. From this panel, you can open the core data sheet that is in PDF format which contains a complete description of the core, its pinouts, parameters, and other technical and ordering information (if is not included free with the core generator). Direct links to IP Center, support and xilinx.com

Customizing a CORE GUI with Dynamic Symbols and Parameterizable Fields
If you select the Generate option to generate the specified core, you are presented with the Parameter screen that contains the Dynamic Symbol on the left. Note the pins that are highlighted in red are pins that are activated as a result of parameter selections on the right. For this demonstration we have selected a Bit Bus Gate Core. If we go down to the Output Options section, you will notice that Non-Registered has been selected. Note the highlighted pins for this set of options. If we change the selection to Both, you will notice that the highlighted pins change and the the Register Options button becomes activated, enabling more customization in the pop-up Register Options window..

CORE Generator Design Flow
Design Entry Design Verification User Design (HDL or Schematic) Symbol Functional Simulation CORE Generator System Simulation Model Synthesis (User design only) CORE Generator Output Files Netlist Timing Simulation Netlist Place & Route Netlist Constraints After you have selected an IP Module, parameterized it, and clicked “generate” the Xilinx CORE Generator will output al ofl the files needed to functionally simulate and implement the IP Module into your current design project directory. Instantiation templates are provided for functional simulation and synthesis. This instantiation template points to a behavioral module. The implementation netlist is provided as an EDIF netlist. Also provided are symbol files that can be used by EDA schematic or block diagrams. Design Implementation

Outputs .EDN (EDIF implementation netlist)
.XCO (core implementation data file / log file) Optional: Foundation or ViewLogic symbols .VEO Verilog template .VHO VHDL template The EDIF file is the actual netlist that is used by the place and route implementation tools. The XCO file is a CORE Generation “log” file which contains all of the parameterization options that were used to create the IP Module. This XCO file can be re-run to recreate the IP Module Optional files, the creation of which will depend on the current CORE Generators project settings, will be the VHDL and Verilog instantiation templates. These templates point to the behavioral models for this IP Module.

Optional Inputs .XCO file .COE file .MIF file
Use as log file and to regenerate module Use to generate module in batch mode .COE file For ROM, RAM, filters Coefficients for filters Memory initialization values .MIF file Specify initialization values for Virtex Block RAM Virtex Block RAM HDL simulation support As indicated the XCO file can be used as an input to re-create the IP Module. The COE and MIF files are used as data inputs for some IP Modules which need coefficient or initialization values.

HDL Behavioral Simulation Flow
Get_models XilinxCoreLib Library Extraction (Do ONCE per IP release) Analyze (VHDL only) xilinxcorelib Generate Module Module Generation & Integration .VEO Instantiate .VHO The IP Modules in the Xilinx CORE Generator have a library of generic behavioral modules which when used are passed the parameter data. This library will need to be extracted for Verilog and analyzed for VHDL. Each time you install new IP Modules, you will need to extract and analyze them into your current HDL libraries. Once this one time behavioral model library setup is complete, when you subsequently run the Xilinx CORE Generator, the HDL templates that are automatically created will have all of the parameter values set for the particular implementation you have selected. .EDN Simulate

Schematic Design Flow Symbol Gen Scripts CORE Generator System .EDN
.ASY .XSF Symbol Gen Scripts Foundation, Mentor, etc... For the Schematic flow, the CORE Generator will create a symbol description file which the EDA schematic tool can use to create a graphical symbol. The symbol will reference the EDIF netlist or alternately point to the HDL template which would point to the behavioral model.

Using the Core Generator Xilinx IP Center Design Reuse & the Core Generator Summary Xilinx IP Center

Xilinx IP Center The Xilinx IP Center was constructed to be the hub of your IP world. This is where you can search for and obtain the very latest versions of cores, and new cores that have been posted since you last installed the Core Generator. These cores can easily be downloaded and updated in your copy of the Core Generator. More about that later. In addition, you can also obtain the latest software updates to the Core Generator itself from the IP Center. There are also useful links to Systems Solutions, links to information about our various partnership programs and links to our Design Reuse tools and methodology, which we will also talk about later. Lets take a look at some of the sorting options. To find the IP you need, you can search by Xilinx IP family. You can also search for IP by a specific vendor, either Xilinx, or our AllianceCORE partners. Or you can search for a specific Technology Solutions, like PCI, , DSP or Reed Solomon. Also note the new link to the Advanced IP Search. Lets take a look at that now.

Xilinx IP Center At the Advanced Search page, we can use the Smart Search search engine to do a more targeted searched for IP. In this example we will pick a TOP Level Category, then a Sub Category within the Top Level Category, and then a specific IP Provider for our search. Expanding the Top Level Categories we select Digital Signal Processing. Expanding the Sub Categories for Digital Signal Processing, we select Filters. Expanding the IP providers we see a list of Xilinx, and all of our AllianceCORE partners that have IP in out IP Center Catalog. For the purpose of this demonstrations, lets select Xilinx. Then we click of the Submit Search button.

Xilinx IP Center Smart Search returns a list of all DSP Filter cores in our catalog that have been developed and are supported by Xilinx. You can drill down by clicking on each one to see the relevant data sheets. The table also displays what type of core it is (Xilinx LogiCORE or partner AllianceCORE), and which Xilinx families of devices are supported by that core. IP Evaluation buttons and purchase buttons are also provided. Most Xilinx IP is free of charge. Xilinx PCI, DSP and Reed Solomon are licensed cores. The BUY button will provide information on obtaining partner AllianceCOREs. Lets see the detail page for the first core.

Xilinx IP Center Here you have your core overview and links to the data sheet for more information and to your try & buy options.

Updating Project Cores Using the IP Center plus the Core Generator
Now lets take a look at how you update your IP using the IP Center and the Core Generator. From the IP Center you would use the “Update Your IP” link to download the latest zip file of IP Updates, and then unzip it in your $Xilinx directory. Then pulling down the Projects, Update IP menu, we see that there are two options to update IP: “All to latest” and “Custom”. All to Latest will update the Core Generator IP if there are any new versions of cores that have been downloaded from the IP Center. Custom allows you to select the cores to update, since you may want to update only specific cores, or you may not want to update certain cores when you are in the middle of a design with those cores. Here we have selected Custom which opens a new Core Generator window, in which we select Fourier Transforms, for example. The Core Generator then displays that there are four cores that have updates available. From here we can put a check mark next to the ones we want to update, and the cores are updated.

Using the Core Generator Xilinx IP Center Design Reuse & the Core Generator Summary Design Reuse & the Core Generator

Design Reuse Leadership
Xilinx IP Capture Tool - IP packaging wizard IP cataloged in Xilinx CORE Generator Internal intra-net distribution of customer IP Design-For-Reuse Information Web based reuse manual Exclusive partnership with Qualis, industry leader Helps project management; verification; qualification Intra-net New Design With so many teams working on FPGA designs it is difficult to keep track of what IP has been created within a company, what IP has been developed by their own team, and what IP needs to be designed. To help solve these issues, the Xilinx IP Capture Tool enables you to use the features of the Xilinx CORE Generator system to catalog and reuse your own IP. The IP Capture tool packages design modules created by individual engineers and enables you to catalog them and make them available to other engineers who are using the Xilinx CORE Generator. The Xilinx IP Capture tool not only provides the ability capture, browse and link to the IP sources code, it allows a designer to package behavioral simulation models, test benches or other simulation vector files as well as PDF or HTML documentation files with the IP core. The core can take the form of synthesizable VHDL or Verilog code, or a fixed function netlist. This “captured” core can be shared over a customer's internal network. Engineers can use at browser to download the IP and install it in their copy of the Xilinx CORE Generator system. Because your internally developed IP can be downloaded and cataloged in the Xilinx CORE Generator, your other design teams will find it easy to browse the IP catalog and find the IP that they need. Design Reuse Methodologies: Xilinx, and Qualis Design Corporation have partnered to provide the industry's first Internet based reuse methodology field guide for both FPGA and ASIC design. The FPGA Reuse Field Guide contains leading design techniques for VHDL and Verilog based designs. Having a common methodology for FPGA and ASIC design allows for easy migration from one technology to another and maximizes the ability to migrate designs between technologies. This migration enables intellectual property to be reused among designers to compress critical time out of the production cycle. The Xilinx FPGA Reuse Field Guide, is more than just a coding style guide. It provides an overview of the economic issues involved with design reuse, detailed information about project specifications, project management and organization, and project verification and qualification.

Xilinx Resources Summary
Web Xilinx IP Center / IPcenter Links to all available cores resources available CORE Generator & IP modules tech tips Links to known issues, documentation and data sheets (general issues) (generic CORE Generator issues) (DSP-specific questions) To summarize the Xilinx resources that are available, you have seen some of the IP Center functions today. Go to to take a closer look at these and other functions that are available there. Tech tips are also available on the web. You can navigate through the web site or go directly to the link listed here. For Xilinx customers, three options are available for contacting us for support or questions.

Xilinx CORE Generator Solution Summary
Delivers a complete catalog of IP Includes Xilinx LogiCORE, AllianceCORE, user IP All IP is delivered through the same IP delivery tool Catalog and reuse your IP with the IP Capture Tool Delivers a complete solution Behavioral models, synthesis templates, netlists Smart-IP guarantees performance LogiCOREs automatically support new architectures IP Center delivers the latest free or licensed IP technology Xilinx gives you the advantage with: Faster time-to-market and Lower cost solutions

CORE Generator System V3.1i

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