1. Fast feedback, studies and possible collaborations Alessandro Drago INFN-LNF ILCDR07 Damping Rings R&D Meeting 5-7 March 2007

2. Main topics List of ILC feedback proposed activities with the involved laboratories. Performances of the new FPGA-based feedback system [collaboration PEP-II / KEK / DAFNE] Measurements about rms noise in the feedback loop - discussion if it can produce an increase of the beam vertical emittance. Proposal of a collaboration (in the ILC project) for a new 16-bit system working at 650MHz sampling frequency Looking for larger feedback-related collaborations

3. List of ILC feedback proposed activities (from ActivitiesResources_061010.pdf). The proposing laboratories are: SLAC LBNL KEK INFN-LNF Note: all the above lab’s have already been involved in long collaborations in the past (remote and near)

11. Looking back: the first FB collaboration This is the longitudinal feedback developed in the years 1992-1996 by a SLAC – LBNL - LNF collaboration Still working @ PEP-II, DAFNE, ALS Four VME crate: each VME board contains 4 dsp The system can manage up to 80 dsp Each dsp can elaborate up to 32 bunches.

12. Proposed by J.D.Fox @ DAFNE2 Alghero workshop (09/2003)

13. G-proto [D.Teytelman et al] since october 2005 installed on DAFNE, horizontal e+ fb, tested @ PEP-II and KEK. Based on Xilinx Virtex-II Vmic 7750 (VMEbus) connected by 2 USB i/f

14. Gproto upgrade (1-12/9/06) - Hardware: temperature monitors installed on the main components in the module

15. -Software: new operator i/f and more efficient FPGA code

16. EPAC’06 Poster THPCH103

17. II generation digital bunch-by-bunch feedback designed for SuperB factory (collaboration SLAC-KEK-LNF) - Features: - extremely compact - gain & phase digital and remote control - possibility to manage any betatron or synchrotron tunes - robust response to big oscillations @ injection (FIR filter 8/16 taps) - real time parameter monitoring - powerful beam diagnostics - main DSP loop based on FPGA (Field Programmable Gate Array) iGp [D.Teytelman et al.] The new feedback under test at SLAC, KEK and LNF

18. iGP: the feedback (almost) in a single chip

19. Power supply Hard disk unit Personal Computer Feedback board 40cm

20. RF clock, triggers & feedback input/output

21. EPICS operator interface and sw tools ready to run

22. ILCDR feedback design considerations It is important to decouple the feedback system from the type of injected pattern: this means to process every bucket (with or without bunch inside). With this approach the fb has to process h channels [h=harmonic number ~ 15000] The fb system have to be so flexible to be able to work with every possible tunes, from the lowest to the highest

23. ILCDR feedback design considerations In DAFNE we have measured a transverse feedback damping time of 7 ms (i.e. 20 turns) using 2 x 250 W power amplifiers Every power amplifier costs ~ 50k euro and the power section is the 80% of the feedback cost In ILC DR, a feedback damping time of 20 turns will mean the capability to manage ~400 ms -1 instability growth rate To dimension correctly power and budget is necessary to know if this is sufficient

24. Vertical emittance warning ILCDR vertical emittance is very low Feedback are active system, so they can make worse the emittance if the beam size in the plane is very small @ KEK/ATF (Nov. 2005): Fox / Teytelman / Tobyama / Flanagan / Drago state that: “RMS noise coming from pickups can enter in the feedback loop to increase the beam vertical dimension and as conseguence the vertical emittance” @ Dafne (Dec. 2006): Fox / Drago make measurements of rms noise sources in the longitudinal feedbacks

25. Noise from pickup @ low frequencies (no beam!)

26. Possible noise sources in the feedback loop

27. Looking for new collaboration/ items to discuss: System specifications R&D on front end analog blocks (T & L) R&D on the digital part R&D on back end analog blocks (T & L) Transverse and Longitudinal kicker design Low noise issue

28. Preliminary proposed specifications for the digital part iGP (today)  ILCDR Feedback F samp : 500MHz  650Mhz Bunch spacing: 2ns  1.5 ns # bunches: ~5000  ~15000 bits processing: 8(12)  16 Filter: 16-taps FIR  50-taps FIR Filter banks: 2  2 Downsampling 1:32  1:32 Fpga Virtex-II  Virtex-5

29. For example the Xilinx Virtex-4 is a fpga low cost module: it can be used to test the software implementation

30. Conclusions A multi-laboratories collaboration is hopeful SLAC, LBNL, KEK, Frascati have a long fruitful story in feedback collaboration It would be very useful to make convergent efforts Test new feedback system on many different colliders or light sources is very stimulating and rich of new suggestions and ideas