0. CBRAM® Macro Embedded in a Body Sensor Node
Nad Gilbert1, Yanqing Zhang2, John Dinh1, Benton Calhoun2,and Shane Hollmer1
1 Adesto Technologies, Sunnyvale, CA 2 University of Virginia, Charlottesville, VA
Hello and thank you for your time this day. My Name in Nad Gilbert and I will be presenting a CBRAM macro embedded in a body sensor node. The CBRAM macro was developed by Adesto technologies and the Body sensor node was contributed by Benton Calhoun and his team at University of Virginia. 0.5min
Turn in By May 23rd to Present on Friday June 14 8:55-9:20 Program # c16-2, session C16 Embedded Non-Volatile Memory

1. Outline Introduction - Ultra Low Power (ULP) CBRAM technology
CBRAM Macro Architecture
Energy Monitor
Sensing Circuit and Energy measurement Results
Write Circuit and Energy measurement Results
Body Sensor Node (BSN) concept and results
Die Photo
Comparison of macro to Prior work
Conclusion
In this Presentation I will introduce the need for CBRAM in ULP systems, briefly discuss the CBRAM technology and then demonstrate the design. I’ll start with the CBRAM Macro Architecture then show the on chip energy monitor used to collect much of the data, the sensing circuit and write circuit along with energy measurement data will follow. I will then show the body sensor node concept and results after which I will show the die photo. We conclude with a comparison to Prior work and some conclusions. ~0.5min

2. Introduction Non-volatile Serial Flash
Typical Low Power Sensor
Non-volatile Serial Flash
The Missing ULP component
TI SoC - Microcontroller, 12 bit ADC, temperature sensor (Demonstrated in ULP system),
128KB embedded FLASH
(The Missing ULP component)
Transceiver (Demonstrated in ULP system)
Sensors are everywhere and with the explosion of devices connected to the internet, their use will dramatically increase in the near future. The application space will be vast from product maintenance and defense to smart homes and health care. This is a photo of a typical low power sensor. The key components of these systems are the transceiver, sensor interface , DSP, digital control (all integrated in this SOC) and memory in both the SOC and serial flash device. Both the transceiver and most of the SOC have been demonstrated in ULP systems, less than 1V, except for the NVM. For these systems to truly accomplish their end use, they need non volatile storage to retain vital data during inevitable loss of power. Today we will demonstrate that CBRAM fills the need for an ULP NVM. 1min
Image courtesy of University of Washington
Slide 2

3. CBRAM Technology – Introduction
< 20nm dimensions
< 0.6V Operation
Multi Level Cell
< 1mA Write
< 0.6V Write
Conductive Bridging RAM (CBRAM) is a subset of Resistive RAM
that is highly
scalable
low power
high performance
and can be integrated at
Back-End-of-Line in a standard
CMOS processes.
First here is a quick introduction to CBRAM technology. Read slide ~0.5min
1Transistor – 1 Resistor Cell (1T1R)
DRAM Cost Structure
<50ns Write
Large Read Signal
Verify During Write
Slide 3

4. CBRAM Technology – Cross section
Data is stored by modulating the resistance of the dielectric layer.
Anode
Cathode
TEM
Here is an example diagram of the CBRAM stack integration into a standard CMOS flow similar to the processes used for this work. The CBRAM cell is integrated into the metal stack at via. This cell consists of an electrochemically conductive anode to supply ions, a dielectric layer where the formation of the conductive bridge occurs and electrochemically inert cathode. Data is stored by modulating the resistance of the dielectric layer. In the 1T1R cell shown here, the cathode of the device is connected to the drain of the transistor. ~0.5min
Transistor
Slide 4

5. CBRAM Technology - Operation
Program at 600mV and 400nA
1T1R Cell
Anode
Voltage (V)
Tpg=14µs
Cathode
400nA 0V
Erase at 600mV and 200nA
1.2V
Ter=2µs
200nA
Voltage (V)
Next we show an example of the cell operation in an ULP power mode. First we start with the formation of the conductive bridge, or program as labeled here. The red line is the anode voltage which is held constant at 0.6V and the blue line is the cathode which is allowed to modulate because of the transistor acting as a current source which is limited to 400nA here. Zero volts is head across the cell until the current source is allowed to pull down. During this 14us period, the bridge is forming until it finally shorts the anode to cathode causing an IR drop across the current source to be visible. To dissolve the link, or erase the cell, a reverse bias is applied across the cell where the anode is a constant 0.6V and the cathode is pulled up by the transistor acting as a current source again with a 200nA limit. The IR drop seen across the cell is small until the bridge is dissolved and the resistance rises causing the drop across the cell to increase to the supply limit of 1.2V. ~1.5min
Cathode
Anode
Time (µs)
Slide 5

6. CBRAM Macro Architecture
Dual bit line
Maximum device isolation
Dual supply domains
VDD (read) VCC (write)
Maximum usage of VCC
Minimized series resistance
Variable Word Line voltage
For this ULP macro a novel dual bit line architecture was developed. This architecture allows for maximum isolation of the cell while optimizing energy and performance. When a bit line is inactive, both anode and source lines are grounded to allow for maximum isolation. There is a BL for the anode connection and another for the source line of the isolation transistor. All of the periphery is operated at VDD, 0.4V while only the write drivers operate at the VCC level, 0.6V The bipolar operation of the cell in concert with the dual bit line architecture allows for maximum usage of the write supply voltage. The drivers interface directly with the bit lines to reduce series resistance which is critical for optimum erase energies. The word line voltage is also variable allowing for lower voltages to limit the programming current and higher values to reduce the series resistance in the erase path. ~1.5min
Slide 6

7. Voltage Across Cell ERASE HALF SEL BL 0 V 0 V 0.6 V 0.6 V 0.4V 0.6 V
PROGRAM
READ
0.6 V
~0.2V
0.4 V
0.4V
Here is a pictorial representation of the voltage expected across the cells in each operation. During erase, the word line voltage is set at 0.6V while the anode is grounded and the source line is also set at 0.6V. During program, the opposite voltages are forced on the anode and cathode while a lower voltage is force on the word line to set the on resistance. The ability to set the on resistance of the cell by limiting the programming current is another key aspect of CBRAM making it compatible with ULP systems. The increased on resistance reduces power not only during program but during erase and read. In the read operation, sub vt source follower force about n 0.2V at the anode and the source line is grounded. The word line is set at 0.4V to reduce power. The half selected cell has the WL voltage on the gate but the anode and cathode are grounded keeping the cell completely isolated. ~2min
0 V
0 V
Slide 7

8. On Chip Energy Monitor VCCANALOG VREF Id(M1)=ILOAD M1 VMEAS
Dynamic Current monitor
VLOAD ILOAD
IBIAS
IBIAS
In order to measure the energy dynamically of single bit and byte operations, each of the supplies, VCC, VDD and VWL where implemented with this regulator. The load and bias current is mirrored to the measurement side of the circuit. On the measurement side, another amplifier regulates the current in M1 to maintain Vload at the drain of M1. This allows for the drain current of M1 to be equal to the load current. The gate voltage is then driven out to the pad to monitor the current. Calibration modes where also implemented to measure the ID vs. VGS curve of M1 to allow for the translation of the measurement voltage into the load current. With a dynamic measurement of the current, the actual energy can then be calculated rather than an average. ~1.5min
Energy monitor for each supply: VCC, VDD, and VWL
Slide 8

9. Sensing Circuit Programmable Pull up VDD as low as 0.3V SN
Pull Up Strength
Programmable Pull up
VDD as low as 0.3V
Read Strobe SN
Data Out
Read Strobe
Source follower Voltage limit
Read Strobe
8:1
8:1
BLS
In this low power design, we chose the simplified current sensing technique. This simplified approach allows for operation at every low VDD levels. A variable pull-up is to compensate for array leakage and allow for a range of on resistances. The initial state keeps the sense node at ground the comparator in the off state. When the read strobe goes high, the select source follower is enabled which forces about VDD/2 across the bit. The source follower also allows the pull up devices to work against the selected cell. The current of the pull up devices vary from 140nA to 2.2uA. If the cell resistance is low, it will pull the SN node below the threshold of the comparator, which is about VDD/2. If it high, the pull up device will pull SN high and increased resistance of the source follower will limit the effect of the BL capacitance on the SN node allowing improvement in the sensing performance. When the read strobe goes low, the date is latched. ~2min
BLAN WL
Slide 9

10. Measured results of Sense circuit
0.39 pJ/B
Using the energy monitor, the energy and delay data was obtained for 3 different strength levels. This further demonstrates the flexibility of the read operation across the different programmed resistances. At the highest supported resistance point, the read energy is 0.39pJ/Byte or 49fJ/bit. ~1min
Slide 10

11. Complete Isolation when not selected
Write Circuit
VCC as low as 0.6V
Minimized Series resistance write path
VCC
VCC
Data Dependent Program
DinPROG 1
drivers
Data Dependent Erase 1
OFF 1
DinERASE
VWL WL
The write circuit controls the voltage on the word line, anode and source line or the cathode of the device. A driver per bit line was implemented to keep the series resistance as low as possible. There are only 3 devices in the signal path at all times. To operate like most NVM, the erase and program operations are data dependent. The BLAN is pulled high during program and held low all other times except during read where the anode is driven by the read circuit. The source line BLS, is driven high during erase and held low at all other times. ~1.5min
BLAN
BLS
Complete Isolation when not selected
Slide 11

12. Measured Results of Program Operation
Measured Program from CBRAM Array
VCC=0.6V, VWL=0.6V, VDD=0.4V
TPROG=
10us
VMEAS (V), α IPROG
Meas. Tot. E (pJ)
leakage
Current
Here the output of the energy monitor output during programming is shown along with the calculated energy. This initial spike is mainly the charging of the BL capacitance to the VCC level. Notice the very little current is observed until the device program as marked here by Tprogram. After the device programs we see a significant increase in current flow which is primarily limited by the voltage on the word line. By using programming detection circuit and algorithms, this post program event energy can be mitigated. ~1.5min
Time (μs)
Slide 12

13. Program Energy vs. Supply
Sim. Energy/bit to PROG const Ron
Energy Minima
at 1V
Energy (pJ)
Energy Minima
at 0.7V
To demonstrate the flexibility of this technology in optimizing energy we show the energy usage as a function of supply to 2 on resistances. The energy levels here include the current drawn from all 3 supplies, VDD, VCC and VWL. Here we show an on resistance of 62k, the blue line, and 300k, the read line. Clearly the higher on resistance produces the lower energy and would be set by reducing the WL voltage. Notice that and energy minimum is much lower for the 300k RON versus the 62.1k ron. The minimum is many produced by the unique voltage time characteristics of the cell. The programming time is exponentially related to the voltage across the cell where large voltage have faster programming times. At larger voltages, however, the energy of the periphery begin to dominate increasing the energy. ~2min
VCC (V)
Slide 13

14. Measured Results of Write Operation
Measured Erase from CBRAM Array
VCC=0.6V, VWL=1V, VDD=0.4V
TERASE=23us
VMEAS (V), α IERASE
leakage
Current
Meas. Tot. E (pJ)
Here we used the energy monitor to capture an erase event. Notice that the majority of the energy is produced before the erase event because of the current required through the cell to produce enough voltage to erase the cell. After the erase even, the energy is expended by the leakage of the macro. The final spike is cause by the driver driving the source lines back to ground for maximum isolation. ~1min
Time (μs)
Slide 14

15. Erase Energy vs. Supply Sim. Energy/bit to Erase time @ const Ron
High Ron, Low energy
Energy (pJ)
As I showed for program, here is the total energy as a function of supply for 2 RON values pf 62.5k and 602k. Because current runs through the cells for the entire erase time, the on resistance and the time to erase become the dominate factors in the erase energies. For the 62.5k case, the larger the voltage the lower the energy. For the high RON, we can see an energy minimum at about 1V. ~1min
VCC (V)
Slide 15

16. Body Sensor Node (BSN) ClkConfig CBRAM IMEM CBRAM DMEM EnConfig
Bus1[7:0]
Bus2[7:0]
DMEM CONFIG. SCAN CHAIN
IMEM CONFIG. SCAN CHAIN
CBRAM IMEM
CBRAM DMEM
EnConfig
ConfigBits
DIGITAL POWER MANAGER
DMA
SystemClk
GPP RISC PROCESSOR
ADC[7:0]
CLOCK
GEN.
ClkScan
IMEM DEBUG SCAN CHAIN
RR ACCEL.
AFIB
ACCEL.
EnScan
SCAN CHAIN OUT
ScanBits
FIR ACCEL.
ENV DET ACCEL.
The CBRAM macro was embedded with the digital platform of the Body sensor node. The BSN digital platform can perform processing on ECG, EEG and EMG signals. In includes a RIC processor, custom node controller, accelerators for heart rate extraction, atrial fibrillation detection, 30 tap FIR, envelope detection, power management, and scan change control. The CBRAM macro performed the storage function for the instruction and data memories. Each of these memories were implemented with the 64kb macro. ~1.5min
Accel. Clks
ScanOutBits
CBRAM was integrated with the Digital Platform only
Slide 16

17. BSN Results
Enable[5:0]
6’hxx
6’h3E
6’hxx
6’h3E
ClkGt[6:0]
7’hxx
7’h01
7’hxx
7’h01
Rst[6:0]
7’hxx
7’h01
7’hxx
7’h01
Bus1_connect[12:0]
13’hxxxx
13’h1F9F
13’hxxxx
13’h1F9F
Bus2_connect[12:0]
13’hxxxx
13’h17FE
13’hxxxx
13’h17FE
RISC_out[7:0]
8’hxx
8’h80
8’hxx
8’h80
Supply Status/Time
Off/…
On/10:45 AM
Off/…
On/5:55 PM
Here we show the correct operation of the RIC processor by using the scan chain outputs. Note the first data set which matches the second data set which was taken a day later. This demonstrates non volatile storage and successful embedded operation min
Measured scan chain outputs showing correct operation of RISC processor from CBRAM, after power-down all day
Slide 17

18. BSN (digital) and CBRAM Die Photograph
64kb CBRAM IMEM
64kb CBRAM DMEM
Timing Blocks And Config.
Scan Chains
DPM
DMA
RISC
μProc
Scan
Out
ENV
DET
CLK
GEN
Prog. FIR
RR+
AFib
Here is the die Photo of the digital portion of the body sensor node with 2 CBRAM macros cells. -0.5min
Slide 18

19. Comparison of Program Energy
[3]
[6]
1000
[4]
100
Program Energy (pJ)
[5] 10
This work 1
Write Voltage (V)
Here is comparison of program energy and write voltages. Most ULP systems are sub 1V operation where only our work lies and the programming energies are 10 time lower than the best we could find with the STT-MRAM. The current dominate NVM, FLASH, requires very large voltage 10V and high energy. The RERAM re quire the lowest voltage but require a great deal of current because of the high currents which is also true of phase change. ~1min
[3] 0.5V 4Mb embedded ReRAM
[4] Flash with self-aligned split-gate cell
[5] STT-MRAM
[6] 4Mb embedded phase-change memory
Slide 19

20. Comparison of Technology
Metric
This work
[3]
[4]
[5]
[6]
Technology
CBRAM
ReRAM
FG Flash
MRAM
PCM
CMOS Compatibility
Yes No
Read Core Voltage (V)
0.35
0.32
0.5
1.2
Write Core Voltage (V)
0.6
2.0 10
3.3
2.8
Program Energy/bit
1 pJ
2 nJ
100 pJ
10 pJ
250 pJ
Read Energy/bit
50 fJ
75 fJ
500 fJ
100 fJ
Charge pumps needed for <1 V SoC
Here is a table for further comparison. As you can see, CBRAM out performs the competition in write voltage and energy. We also have a lower energy read and have demonstrated lower voltage reads comparable with ReRAM. CBRAM is the only truly compatible technology with sub 1 V SoC and is also compatible with standard CMOS processes. ~1min
Slide 20

21. Conclusion Device Technology Array size Operating voltage
2 CBRAM macros embedded in BSN
Technology
0.13 mm standard CMOS
Array size
64 kb
Operating voltage
Integrated in BSN 0.5V
CBRAM macro 0.4 V read 0.6 V write
Operating Frequency
200 kHz
Write energy
8 pJ
In conclusion, we demonstrated 2 CBRAM macros embedded in a BSN in standard 0.13um CMOS process. The array size was 64kb and the operation voltage in the BSN was 0.5V and 0.4V or read and 0.6V for write in the macro. The system operated at 200kHz and the write energy was 8 pJ. -0.5min
Slide 21

22. Acknowledgements Ralph Williams and Derric Lewis Altis Semiconductor
Digital test interface of the CBRAM macro
Altis Semiconductor
Chip manufacturing
DARPA
Partial funding through an SBIR award
~0.5min
Slide 22