1. Computer Architecture I: Digital Design Dr. Robert D. Kent Logic Design Decoders and Multiplexers

2. Review We have begun to study logic design in the contexts of Medium Scale Integration (MSI) of gate devices and programmable logic devices (PLD). We have studied the design of a number of specific, practical functional circuits, expressed in terms of Boolean expressions and their equivalent logic gates (SSI: Small Scale Integration) with a view to re-using those circuits as components in MSI design. –1-bit Half-Adder 1-bit Full-Adder –Multi-bit Ripple AdderSubtractor –Decade AdderComparator

3. Goals We continue our study of simple, but functional Combinational circuits, namely Decoders/Encoders, Multiplexers, and PLD/PLA circuits: –we continue constructing a small library of useful components –through study of the solution process using Boolean algebra and Boolean calculus (simplification, etc.) we better understand the meaning of SSI design –we seek to identify these components for their re-use potential –through our study we will better understand how MSI increases the level of abstraction in solving problems - SSI design is relatively concrete.

4. Circuit # 9 : Decoders

5. Decoders are most often used to transform one type of coding to another. –Change data representations –Design of address bus networks (specify an address to obtain data)

6. Circuit # 9 : Decoders Decoders are most often used to transform one type of coding to another. –Change data representations –Design of address bus networks A decoder is a multi-input, multi-output logic network.

7. Circuit # 9 : Decoders Decoders are most often used to transform one type of coding to another. –Change data representations –Design of address bus networks A decoder is a multi-input, multi-output logic network. –Typically with N inputs and 2 N outputs. N-to-2 N 0 DEC 0 1 1 2 2...... N-1 2 N -1

8. Circuit # 9 : Decoders Decoders are most often used to transform one type of coding to another. –Change data representations –Design of address bus networks A decoder is a multi-input, multi-output logic network. –Typically with N inputs and 2 N outputs. Other types of N-to-M decoders are also used, where M < 2 N. N-to-2 N 0 DEC 0 1 1 2 2...... N-1 2 N -1

9. Circuit # 9a : Simple Decoder The simplest decoder has N inputs and 2 N outputs. –The set of all N inputs is interpreted as an unsigned binary number that, in turn, selects a particular output line to output a value 1 with all other output lines having value 0.

10. Circuit # 9a : Simple Decoder The simplest decoder has N inputs and 2 N outputs. –The set of all N inputs is interpreted as an unsigned binary number that, in turn, selects a particular output line to output a value 1 with all other output lines having value 0. Example: a 2-line input to 4-line output decoder

11. Circuit # 9a : Simple Decoder The simplest decoder has N inputs and 2 N outputs. –The set of all N inputs is interpreted as an unsigned binary number that, in turn, selects a particular output line to output a value 1 with all other output lines having value 0. Example: a 2-line input to 4-line output decoder Truth table: Label the outputs D K, noting that the subscript value, K, is just the (unsigned) binary value K radix-2 = [x 1 x 0 ]. Only one output line = 1 at a time. x 1 x 0 D 0 D 1 D 2 D 3 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 0 0 0 1

12. Circuit # 9a : Simple Decoder The simplest decoder has N inputs and 2 N outputs. –The set of all N inputs is interpreted as an unsigned binary number that, in turn, selects a particular output line to output a value 1 with all other output lines having value 0. Example: a 2-line input to 4-line output decoder Truth table: Label the outputs D K, noting that the subscript value, K, is just the (unsigned) binary value K radix-2 = [x 1 x 0 ]. Only one output line = 1 at a time. x 1 x 0 D 0 D 1 D 2 D 3 0 0 1 0 0 0 D 0 = x 1 ’ x 0 ’ 0 1 0 1 0 0 D 1 = x 1 ’ x 0 1 0 0 0 1 0 D 2 = x 1 x 0 ’ 1 1 0 0 0 1 D 3 = x 1 x 0

13. Circuit # 9a : Simple Decoder The simplest decoder has N inputs and 2 N outputs. –The set of all N inputs is interpreted as an unsigned binary number that, in turn, selects a particular output line to output a value 1 with all other output lines having value 0. Example: a 2-line input to 4-line output decoder D 0 = x 1 ’ x 0 ’ D 1 = x 1 ’ x 0 D 2 = x 1 x 0 ’ D 3 = x 1 x 0 D0D1D2D3D0D1D2D3 X0X1X0X1 2-to-4 DEC

14. Circuit # 9a : Simple Decoder The simplest decoder has N inputs and 2 N outputs. –The set of all N inputs is interpreted as an unsigned binary number that, in turn, selects a particular output line to output a value 1 with all other output lines having value 0. Example: a 2-line input to 4-line output decoder D 0 = x 1 ’ x 0 ’ D 1 = x 1 ’ x 0 D 2 = x 1 x 0 ’ D 3 = x 1 x 0 D0D1D2D3D0D1D2D3 X0X1X0X1 2-to-4 DEC Note: Buffer-Inverter =

15. Circuit # 9b : Simple Decoder The simplest decoder has N inputs and 2 N outputs. –The set of all N inputs is interpreted as an unsigned binary number that, in turn, selects a particular output line to output a value 1 with all other output lines having value 0. We consider the example of a 3-input, 8-output decoder.

16. Circuit # 9b : Simple Decoder The simplest decoder has N inputs and 2 N outputs. –The set of all N inputs is interpreted as an unsigned binary number that, in turn, selects a particular output line to output a value 1 with all other output lines having value 0. We consider the example of a 3-input, 8-output decoder. x 2 x 1 x 0 z 0 z 1 z 2 z 3 z 4 z 5 z 6 z 7 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 1

17. Circuit # 9b : Simple Decoder The simplest decoder has N inputs and 2 N outputs. –The set of all N inputs is interpreted as an unsigned binary number that, in turn, selects a particular output line to output a value 1 with all other output lines having value 0. We consider the example of a 3-input, 8-output decoder. x 2 x 1 x 0 z 0 z 1 z 2 z 3 z 4 z 5 z 6 z 7 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 1 Note that each output, Z J, is characterized by a single 1-value that can be immediately represented as a single minterm.

18. Circuit # 9b : Simple Decoder The simplest decoder has N inputs and 2 N outputs. –The set of all N inputs is interpreted as an unsigned binary number that, in turn, selects a particular output line to output a value 1 with all other output lines having value 0. We consider the example of a 3-input, 8-output decoder. x 2 x 1 x 0 z 0 z 1 z 2 z 3 z 4 z 5 z 6 z 7 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 1 Z 0 = X 2 X 1 X 0 Z 1 = X 2 X 1 X 0 Z 2 = X 2 X 1 X 0 Z 3 = X 2 X 1 X 0 Z 4 = X 2 X 1 X 0 Z 5 = X 2 X 1 X 0 Z 6 = X 2 X 1 X 0 Z 7 = X 2 X 1 X 0 3-to-8 DEC 0 0 1 2 1 3 4 2 5 6 7 X0X1X2X0X1X2

19. Circuit # 9b : Simple Decoder The simplest decoder has N inputs and 2 N outputs. –The set of all N inputs is interpreted as an unsigned binary number that, in turn, selects a particular output line to output a value 1 with all other output lines having value 0. We consider the example of a 3-input, 8-output decoder. x 2 x 1 x 0 z 0 z 1 z 2 z 3 z 4 z 5 z 6 z 7 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 1 Z 0 = X 2 X 1 X 0 Z 1 = X 2 X 1 X 0 Z 2 = X 2 X 1 X 0 Z 3 = X 2 X 1 X 0 Z 4 = X 2 X 1 X 0 Z 5 = X 2 X 1 X 0 Z 6 = X 2 X 1 X 0 Z 7 = X 2 X 1 X 0 3-to-8 DEC 0 0 1 2 1 3 4 2 5 6 7 X0X1X2X0X1X2 minterms

20. Circuit # 9b : Simple Decoder The decoder that we have developed is called a minterm generator decoder.

21. Circuit # 9b : Simple Decoder The decoder that we have developed is called a minterm generator decoder. This type of MSI circuit is particularly valuable for constructing other types of circuits, based on the use of minterm expressions:

22. Circuit # 9b : Simple Decoder The decoder that we have developed is called a minterm generator decoder. This type of MSI circuit is particularly valuable for constructing other types of circuits, based on the use of minterm expressions: –Example: Consider two functions F( X 2 X 1 X 0 ) = Sum m(1,2,4,5) G( X 2 X 1 X 0 ) = Sum m(1,5,7)

23. Circuit # 9b : Simple Decoder The decoder that we have developed is called a minterm generator decoder. This type of MSI circuit is particularly valuable for constructing other types of circuits, based on the use of minterm expressions: –Example: Consider two functions F( X 2 X 1 X 0 ) = Sum m(1,2,4,5) G( X 2 X 1 X 0 ) = Sum m(1,5,7) –These can be constructed immediately using the decoder and or gates.

24. Circuit # 9b : Simple Decoder The decoder that we have developed is called a minterm generator decoder. This type of MSI circuit is particularly valuable for constructing other types of circuits, based on the use of minterm expressions: –Example: Consider two functions F( X 2 X 1 X 0 ) = Sum m(1,2,4,5) G( X 2 X 1 X 0 ) = Sum m(1,5,7) –These can be constructed immediately using the decoder and or gates. F 3-to-8 DEC 0 0 1 2 1 3 4 2 5 6 7 X0X1X2X0X1X2 G

25. Circuit # 9c : Simple Decoder We note that various functions can be transformed from one form to another.

26. Circuit # 9c : Simple Decoder We note that various functions can be transformed from one form to another. For example: H( X 2 X 1 X 0 ) = Sum m(0,3,6,7)

27. Circuit # 9c : Simple Decoder We note that various functions can be transformed from one form to another. For example: H( X 2 X 1 X 0 ) = S m(0,3,6,7) = S m(0,3,6,7) double complement

28. Circuit # 9c : Simple Decoder We note that various functions can be transformed from one form to another. For example: H( X 2 X 1 X 0 ) = S m(0,3,6,7) = S m(0,3,6,7) double complement = S m(1,2,4,5) complement canonical minterm

29. Circuit # 9c : Simple Decoder We note that various functions can be transformed from one form to another. For example: H( X 2 X 1 X 0 ) = S m(0,3,6,7) = S m(0,3,6,7) double complement = S m(1,2,4,5) complement canonical minterm = F( X 2 X 1 X 0 )

30. Circuit # 9c : Simple Decoder We note that various functions can be transformed from one form to another. For example: H( X 2 X 1 X 0 ) = S m(0,3,6,7) = G m(0,3,6,7) double complement = S m(1,2,4,5) complement canonical minterm = F( X 2 X 1 X 0 ) H 3-to-8 DEC 0 0 1 2 1 3 4 2 5 6 7 X0X1X2X0X1X2 G

31. Circuit # 9c : Simple Decoder We note that various functions can be transformed from one form to another. For example: H( X 2 X 1 X 0 ) = S m(0,3,6,7) = G m(0,3,6,7) double complement = S m(1,2,4,5) complement canonical minterm = F( X 2 X 1 X 0 ) H 3-to-8 DEC 0 0 1 2 1 3 4 2 5 6 7 X0X1X2X0X1X2 G Note the inverter on the output H, equivalent to using a nor gate.

32. Circuit # 9d : Decoders with Enable Input Normally, decoders have one or more additional input lines referred to as enable inputs. –These line values determine whether the circuit is operational or not.

33. Circuit # 9d : Decoders with Enable Input Normally, decoders have one or more additional input lines referred to as enable inputs. –These line values determine whether the circuit is operational or not. Example: a 2-to-4 decoder with enable input Truth table: Outputs D K can only have value 1 if enabled, E = 1. E x 1 x 0 D 0 D 1 D 2 D 3 0 - - 0 0 0 0 Note: x 1 x 0 don’t matter 1 0 0 1 0 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 0 1 1 1 0 0 0 1

34. Circuit # 9d : Decoders with Enable Input Normally, decoders have one or more additional input lines referred to as enable inputs. –These line values determine whether the circuit is operational or not. Example: a 2-to-4 decoder with enable input Truth table: Outputs D K can only have value 1 if enabled, E = 1. E x 1 x 0 D 0 D 1 D 2 D 3 0 - - 0 0 0 0 Note: x 1 x 0 don’t matter 1 0 0 1 0 0 0 D 0 = E x 1 ’ x 0 ’ 1 0 1 0 1 0 0 D 1 = E x 1 ’ x 0 1 1 0 0 0 1 0 D 2 = E x 1 x 0 ’ 1 1 1 0 0 0 1 D 3 = E x 1 x 0

35. Circuit # 9d : Decoders with Enable Input Example: a 2-to-4 decoder with enable input D 0 = E x 1 ’ x 0 ’ D 1 = E x 1 ’ x 0 D 2 = E x 1 x 0 ’ D 3 = E x 1 x 0 D0D1D2D3D0D1D2D3 X0X1X0X1 2-to-4 DEC E On(1) Off(0)

36. Circuit # 9d : Decoders with Enable Input Example: a 2-to-4 decoder with enable input D 0 = E x 1 ’ x 0 ’ D 1 = E x 1 ’ x 0 D 2 = E x 1 x 0 ’ D 3 = E x 1 x 0 D0D1D2D3D0D1D2D3 X0X1X0X1 2-to-4 DEC E On(1) Off(0) D0D1D2D3D0D1D2D3 X0X1X0X1 E 2-to-4 DEC

37. Circuit # 9e : Decoder as LED Controller We now consider using a decoder to control the output of a set of light emitting diodes (LED’s) that display a decimal digit. LED digit

38. Circuit # 9e : Decoder as LED Controller We now consider using a decoder to control the output of a set of light emitting diodes (LED’s) that display a decimal digit. We use a 4-to-7 decoder with enable input (E = 1 ON, E = 0 OFF) LED digit 1 0 2 3 54 6

39. 1 0 2 3 54 6 Circuit # 9e : Decoder as LED Controller We now consider using a decoder to control the output of a set of light emitting diodes (LED’s) that display a decimal digit. We use a 4-to-7 decoder with enable input (E = 1 ON, E = 0 OFF) E x 3 x 2 x 1 x 0 z 0 z 1 z 2 z 3 z 4 z 5 z 6 0 - - - - 0 0 0 0 0 0 0 LED digit

40. 1 0 2 3 54 6 Circuit # 9e : Decoder as LED Controller We now consider using a decoder to control the output of a set of light emitting diodes (LED’s) that display a decimal digit. We use a 4-to-7 decoder with enable input (E = 1 ON, E = 0 OFF) E x 3 x 2 x 1 x 0 z 0 z 1 z 2 z 3 z 4 z 5 z 6 0 - - - - 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 1 1 1 LED digit

41. 1 0 2 3 54 6 Circuit # 9e : Decoder as LED Controller We now consider using a decoder to control the output of a set of light emitting diodes (LED’s) that display a decimal digit. We use a 4-to-7 decoder with enable input (E = 1 ON, E = 0 OFF) E x 3 x 2 x 1 x 0 z 0 z 1 z 2 z 3 z 4 z 5 z 6 0 - - - - 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 1 1 1 1 0 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 1 0 1 1 1 0 1 1 0 0 1 1 1 0 1 1 0 1 1 LED digit

42. 1 0 2 3 54 6 Circuit # 9e : Decoder as LED Controller We now consider using a decoder to control the output of a set of light emitting diodes (LED’s) that display a decimal digit. We use a 4-to-7 decoder with enable input (E = 1 ON, E = 0 OFF) E x 3 x 2 x 1 x 0 z 0 z 1 z 2 z 3 z 4 z 5 z 6 0 - - - - 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 1 1 1 1 0 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 1 0 1 1 1 0 1 1 0 0 1 1 1 0 1 1 0 1 1 1 0 1 0 0 0 1 1 1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 1 LED digit

43. 1 0 2 3 54 6 Circuit # 9e : Decoder as LED Controller We now consider using a decoder to control the output of a set of light emitting diodes (LED’s) that display a decimal digit. We use a 4-to-7 decoder with enable input (E = 1 ON, E = 0 OFF) E x 3 x 2 x 1 x 0 z 0 z 1 z 2 z 3 z 4 z 5 z 6 0 - - - - 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 1 1 1 1 0 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 1 0 1 1 1 0 1 1 0 0 1 1 1 0 1 1 0 1 1 1 0 1 0 0 0 1 1 1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 1 1 0 1 1 0 0 1 0 1 1 1 1 1 0 1 1 1 1 0 1 0 0 1 0 1 1 0 0 0 1 1 1 1 1 1 1 LED digit

44. 1 0 2 3 54 6 Circuit # 9e : Decoder as LED Controller We now consider using a decoder to control the output of a set of light emitting diodes (LED’s) that display a decimal digit. We use a 4-to-7 decoder with enable input (E = 1 ON, E = 0 OFF) E x 3 x 2 x 1 x 0 z 0 z 1 z 2 z 3 z 4 z 5 z 6 0 - - - - 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 1 1 1 1 0 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 1 0 1 1 1 0 1 1 0 0 1 1 1 0 1 1 0 1 1 1 0 1 0 0 0 1 1 1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 1 1 0 1 1 0 0 1 0 1 1 1 1 1 0 1 1 1 1 0 1 0 0 1 0 1 1 0 0 0 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 0 1 0 LED digit

45. Circuit # 9e : Decoder as LED Controller We obtain the canonical minterm expressions: E x 3 x 2 x 1 x 0 z 0 z 1 z 2 z 3 z 4 z 5 z 6 0 - - - - 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 1 1 1 1 0 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 1 0 1 1 1 0 1 1 0 0 1 1 1 0 1 1 0 1 1 1 0 1 0 0 0 1 1 1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 1 1 0 1 1 0 0 1 0 1 1 1 1 1 0 1 1 1 1 0 1 0 0 1 0 1 1 0 0 0 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 0 1 0

46. Circuit # 9e : Decoder as LED Controller We obtain the canonical minterm expressions: E x 3 x 2 x 1 x 0 z 0 z 1 z 2 z 3 z 4 z 5 z 6 0 - - - - 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 1 1 1 1 0 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 1 0 1 1 1 0 1 1 0 0 1 1 1 0 1 1 0 1 1 1 0 1 0 0 0 1 1 1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 1 1 0 1 1 0 0 1 0 1 1 1 1 1 0 1 1 1 1 0 1 0 0 1 0 1 1 0 0 0 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 0 1 0 Z 0 = S m(0,2,3,5,7,8,9) Z 1 = S m(0,4,5,6,8,9) Z 2 = S m(0,1,2,3,4,7,8,9) Z 3 = S m(2,3,4,5,6,8,9) Z 4 = S m(0,2,6,8) Z 5 = S m(0,1,2,4,5,6,7,8,9) Z 6 = S m(0,2,3,5,6,8)

47. Circuit # 9e : Decoder as LED Controller And simplify, if possible (e.g. using complementation): E x 3 x 2 x 1 x 0 z 0 z 1 z 2 z 3 z 4 z 5 z 6 0 - - - - 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 1 1 1 1 0 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 1 0 1 1 1 0 1 1 0 0 1 1 1 0 1 1 0 1 1 1 0 1 0 0 0 1 1 1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 1 1 0 1 1 0 0 1 0 1 1 1 1 1 0 1 1 1 1 0 1 0 0 1 0 1 1 0 0 0 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 0 1 0 Z 0 = S m(0,2,3,5,7,8,9) Z 1 = G m(0,4,5,6,8,9) Z 2 = G m(0,1,2,3,4,7,8,9) Z 3 = G m(2,3,4,5,6,8,9) Z 4 = G m(0,2,6,8) Z 5 = G m(0,1,2,4,5,6,7,8,9) Z 6 = G m(0,2,3,5,6,8) Z 0 ’ = S m(1,4,6) Z 1 ’ = S m(1,2,3,7) Z 2 ’ = S m(5,6) Z 3 ’ = S m(0,1,7) Z 4 ’ = S m(1,3,4,5,7,9) Z 5 ’ = S m(3) Z 6 ’ = S m(1,4,7,9)

48. Z 0 ’ = S m(1,4,6) Z 1 ’ = S m(1,2,3,7) Z 2 ’ = S m(5,6) Z 3 ’ = S m(0,1,7) Z 4 ’ = S m(1,3,4,5,7,9) Z 5 ’ = S m(3) Z 6 ’ = S m(1,4,7,9) Circuit # 9e : Decoder as LED Controller X0X1X2X3EX0X1X2X3E 4-to-10 DEC 0 0 1 1 2 2 3 3 4 5 6 7 8 9 Z0’Z1’Z2’Z3’Z4’Z5’Z6’Z0’Z1’Z2’Z3’Z4’Z5’Z6’ 1 0 2 3 54 6

49. Circuit # 10 : Encoders

50. Encoders are essentially the inverse of decoders. Typical encoders are represented as 2 N input lines to N output lines. In general, encoders are N-to-M decoders, where N > M. 2 N -to-N 0 ENC 0 1 1 2 2...... 2 N -1 N-1 N-to-2 N 0 DEC 0 1 1 2 2...... N-1 2 N -1

51. Circuit # 11 : Multiplexers

52. Multiplexers are used in many places within computers. One important use is in designing and constructing data buses. I0I1I2I3EI0I1I2I3E S 1 S 0 F 4-to-1 MUX

53. Circuit # 11 : Multiplexers Multiplexers are used in many places within computers. One important use is in designing and constructing data buses. For this reason they are also called data selectors. I0I1I2I3EI0I1I2I3E S 1 S 0 F 4-to-1 MUX

54. Circuit # 11 : Multiplexers Multiplexers are used in many places within computers. One important use is in designing and constructing data buses. For this reason they are also called data selectors. Assuming that data exists in 2 N locations, I 0, I 1, … etc., the objective of the circuit is to obtain a copy of the data value, I K, at the output, F. I0I1I2I3EI0I1I2I3E S 1 S 0 F 4-to-1 MUX

55. Circuit # 11 : Multiplexers Multiplexers are used in many places within computers. One important use is in designing and constructing data buses. For this reason they are also called data selectors. Assuming that data exists in 2 N locations, I 0, I 1, … etc., the objective of the circuit is to obtain a copy of the data value, I K, at the output, F. The data value, I K, is selected using the selector inputs, S J, similar to the operation of the decoder. I0I1I2I3EI0I1I2I3E S 1 S 0 F 4-to-1 MUX

56. Circuit # 11 : Multiplexers Multiplexers are used in many places within computers. One important use is in designing and constructing data buses. For this reason they are also called data selectors. Assuming that data exists in 2 N locations, I 0, I 1, … etc., the objective of the circuit is to obtain a copy of the data value, I K, at the output, F. The data value, I K, is selected using the selector inputs, S J, similar to the operation of the decoder. The multiplexer, or MUX, may be enabled/disabled. I0I1I2I3EI0I1I2I3E S 1 S 0 F 4-to-1 MUX

57. Circuit # 11 : Multiplexers The details of the circuit are easily derived and laid out in the form: I0 I1 I2 I3 S1 S0 F E I0I1I2I3EI0I1I2I3E F 4-to-1 MUX

58. Circuit # 11 : Multiplexers The details of the circuit are easily derived and laid out in the form: I0 I1 I2 I3 S1 S0 0 0 I0I1I2I3EI0I1I2I3E F 4-to-1 MUX Disabled MUX

59. Circuit # 11 : Multiplexers The details of the circuit are easily derived and laid out in the form: I0I1I2I3EI0I1I2I3E S 1 S 0 F 4-to-1 MUX Enabled MUX I0 I1 I2 I3 1 0 I2 1

60. Circuit # 11 : Multiplexers Example. Consider a data bus intended to fetch 4-bits from a specified address.

61. Circuit # 11 : Multiplexers Example. Consider a data bus intended to fetch 4-bits from a specified address. Address RAM Contents B 3 B 2 B 1 B 0 00B 3 B 2 B 1 B 0 01B 3 B 2 B 1 B 0 10B 3 B 2 B 1 B 0 11

62. Circuit # 11 : Multiplexers Example. Consider a data bus intended to fetch 4-bits from a specified address. Address RAM Contents B 3 B 2 B 1 B 0 00B 3 B 2 B 1 B 0 01B 3 B 2 B 1 B 0 10B 3 B 2 B 1 B 0 11 Each memory unit contains 4 bits. Each bit has an input/output line. Note the important fact that each memory unit has a separate and unique address.

63. Circuit # 11 : Multiplexers Example. Consider a data bus intended to fetch 4-bits from a specified address. Address RAM Contents B 3 B 2 B 1 B 0 00B 3 B 2 B 1 B 0 01B 3 B 2 B 1 B 0 10B 3 B 2 B 1 B 0 11 It is required to copy (obtain) the 4-bits of a specified address to a different output location that can hold 4-bits. We use multiplexers to achieve this goal.

64. Circuit # 11 : Multiplexers Example. Consider a data bus intended to fetch 4-bits from a specified address. Address RAM Contents Means enable is ON. B 3 B 2 B 1 B 0 00B 3 B 2 B 1 B 0 01B 3 B 2 B 1 B 0 10B 3 B 2 B 1 B 0 11 4x1 MUX S 1 S 0 F0F1F2F3F0F1F2F3 First, connect an Nx1 MUX to each of the N bits labeled bit-0, or B 0. Then, add L more such MUX connections to form a complete bus.

65. Circuit # 11 : Multiplexers Example. Consider a data bus intended to fetch 4-bits from a specified address. Address RAM Contents Means enable is ON. B 3 B 2 B 1 B 0 00B 3 B 2 B 1 B 0 01B 3 B 2 B 1 B 0 10B 3 B 2 B 1 B 0 11 4x1 MUX S 1 S 0 4x1 MUX F0F1F2F3F0F1F2F3 The full circuit shows how a data bus architecture may be defined.

66. Circuit # 11 : Multiplexers Example. Consider a data bus intended to fetch 4-bits from a specified address. Address RAM Contents Means enable is ON. B 3 B 2 B 1 B 0 00B 3 B 2 B 1 B 0 01B 3 B 2 B 1 B 0 10B 3 B 2 B 1 B 0 11 4x1 MUX 0 1 4x1 MUX F 0 = B 0 F 1 = B 1 F 2 = B 2 F 3 = B 3 4x1 MUX The highlighted lines show how data selection is achieved. Address selection

67. Circuit # 11 : Multiplexers There are numerous applications of multiplexers in logic design. Review the examples discussed in the textbook –Section 5.6.1 pages 266-276.

68. Summary - Part II We continue to study logic design in the contexts of Small Scale Integration (SSI) and Medium Scale Integration (MSI) of gate devices. We have studied the design of a number of specific, practical functional circuits with a view to re-using those circuits as components in MSI design. Adders Subtractors Comparator We note the differing design approaches, or emphases, effected by differential layering of abstraction. (The same design issue arises in the context of software engineering as well.) SSI: Boolean algebra / Simplification / Logic gates MSI: Interconnection networks / Iterative re-use / Components