1. 12/13/2015445_01 1 Computer Organization EEC-213 Computer Organization Electrical and Computer Engineering

2. 12/13/2015 445_012 Grading  Homework10%  Midterm Exam 10%  Oral Exam 20%  Final Exam60%

3. 12/13/2015 445_013 Honor Code  You are encouraged to discuss homework problems with other students and/or obtain the assistance of the instructor. Nevertheless, homework submissions should be the work of you and your partner.  Exams are closed book, closed notes, no use of calculators, and the normal honor code applies to all exams.

4. 12/13/2015 445_014 Textbooks  Computer Organization, 5th ed. Carl Hamacher, et al., ISBN 0-07-232086-9 2002

5. 12/13/2015 445_015 Questions?

6. Basic structure of Computers 12/13/2015 445_026

7. 12/13/2015 445_017 Processor Computer Functional Units Memory Arithmetic & Logic Control I/O Input Output

8. 12/13/2015 445_018 Course Organization  Computer Structure (Ch 1)  Instruction Sets & Addressing Modes (Ch 2)  Example Computer: Motorola 68000 (Ch 3)  Control Unit Design (Ch 7)  Computer Arithmetic (Ch 6)  Memory (Ch 5)  Input/Output (Ch 4)  Pipelining (Ch 8)

9. 12/13/2015 445_019 Computer Information (Binary)  (Machine) Instructions (Machine Language) Programs  Data 2's complement BCD ASCII

10. 12/13/2015 445_0110  Output Display Printer Speakers I/O  Input Keyboard Mouse Microphone Camera Scanner  Serial Communications Network Modem

11. 12/13/2015 445_0111 Memory  Primary Random Access Memory (RAM) Read Only Memory (ROM)  Organization Word Address Read/Write  Secondary Magnetic Disks Tape Optical Disks  Hierarchy Cache Main Virtual

12. 12/13/2015 445_0112 ALU  Arithmetic Addition Subtraction Multiplication Division Comparison  Logic AND OR NOT XOR  Registers Store Shift

13. 12/13/2015 445_0113 Control Unit  Coordinates/Directs other Units  Computer Operation Input Program/Data stored in Memory Processing Information fetched into Registers Processed by ALU Output

14. 12/13/2015 445_0214 Computer Instructions  Assembly Language MOVE NUM1,R1 MOVE #1,R2 ADD #1,R1 ADD R1,R2  Register Transfer Notation R1  [NUM1] R2  1 R1  1 + [R1] R2  [R1] + [R2]

15. 12/13/2015 445_0215 Processor and Memory ALU IR MAR MEM PC MDR R0R0 R1R1...... R n-1 Control Processor MAR - Memory Address Register MDR - Memory Data Register PC - Program Counter IR - Instruction Register

16. 12/13/2015 445_0216 Example Instruction  Fetch MAR  [PC] PC  [PC] + 1 MDR  [MEM(MAR)] IR  [MDR]  Execute MAR  NUM1 MDR  [MEM(MAR)] R1  [MDR] MOVE NUM1,R1

17. 12/13/2015 445_0217 Another Example  Fetch MAR  [PC] PC  [PC] + 1 MDR  [MEM(MAR)] IR  [MDR]  Execute R1  1 + R1 ADD #1,R1

18. 12/13/2015445_02 18 Single-Bus Structure The computer parts must be connected in some way A group of lines that serves as a connecting path for several devices is called bus Only one transfer at a time can occurs between 2 units Devices includes a buffer register to hold information during transfer MemoryProcessorInputOutput

19. 12/13/2015 445_0219 Single-Bus Architecture (HW1) AB R ALU MDR MAR MEM BUS A Y Z

20. 12/13/2015 445_0220 System Software  Compiler High-level Language  Machine Language  Assembler Assembly Language  Machine Language  Text Editor Keyboard Input  File  Operating System Control Sharing & Interaction Assign & Manage Resources Memory Disk Space Handle I/O

21. Memory Performance  Programs and data are stored in memory  Instruction are fetched one by one over the bus to the processor, and a copy is placed in the cache.  When a data is executed by an instruction a copy is placed in the cache  Later if the same instruction or data item is needed a second time, it’s red directly from the cache.  Execution of instruction and data from the cache is faster than the main memory 12/13/2015 445_0221 Main Memory Processor Cache Memory

22. 12/13/2015 445_0222 Processor Clock  Period (P)  Rate (R) CLK  R = 1/P  1 GHz = 1/1ns

23. 12/13/2015 445_0223 Performance Equation  Processor Execution Time (T)  Number of Machine Language Instructions (N)  Average Steps per Machine Instruction (S)  Clock Rate (R)  Performance of a processor of 2.4 GHz & a processor of 2.8 GHz of another type.

24. 12/13/2015 445_0224 Pipelining F1F1 E1E1 I1I1 F2F2 E2E2 I2I2 F3F3 E3E3 I3I3 Sequential Execution F1F1 E1E1 I1I1 F2F2 E2E2 I2I2 F3F3 E3E3 I3I3 Pipelined Execution

25. 12/13/2015 445_0225 Parallel Processing  Parallel Execution Superscalar ( execution of several instructions in every clock cycle)  Multiprocessors Shared-Memory  Multicomputers Message-Passing

26. 12/13/2015 445_0226 CISC vs RISC  Complex Instruction Set Computers (CISC) Smaller N Larger S  Reduced Instruction Set Computers (RISC) Larger N Smaller S Easier to Pipeline

27. 12/13/2015 445_0127 History  First Generation (miliseconds) von Neumann (stored program) Vacuum Tubes Magnetic Core Memory Teletypes/Magnetic Tapes  Second Generation (microseconds) Transistor High-level Languages (C++, Pascal, Fortran) Compilers (translate HHL to M/C instruction) I/O Processors

28. 12/13/2015 445_0128 History  Third Generation Integrated Circuits Microprogramming Parallelism/Pipelining Operating Systems (sharing) Cache/VM  Fourth Generation (nanoseconds) VLSI (Single Chip Microprocessor) Personal Computers Networks

29. Problem 1-3 Load A,R0 Load B,R1 Add R0,R1 Store R1,C (b) Yes; Move B,C Add A,C 12/13/2015 445_0229

30. 12/13/2015 445_0230 Review  Binary  Hex  2's-complement  Overflow