1. soc 8.1 Chapter 8 What’s Next: Challenges Ahead Computer System Design System-on-Chip by M. Flynn & W. Luk Pub. Wiley 2011 (copyright 2011)

2. soc 8.2 Future (1): Autonomous SOC SOC Consists of multiple heterogeneous processors, controllers and memory but it’s still only a part of a larger system: with power source, disk, network interface, transducers, I/O, actuators (speakers and displays), etc how much of this can we put on a single die? Perhaps all but the actuators

3. soc 8.3 ASOC: what it is a standalone (in so far as possible) SOC with the sensors, actuators, controllers communications and storage capable of realizing complete communications, sense, analysis, recognition and motor actions must be more than simple sense and communicate; analysis to create information

4. soc 8.4 Autonomous (untethered) chips a simplified classification: simple identification of the die itself (as in RFID) with RF response identification of a sensor detected “event” with RF response (as in Smart Dust [Coo] and many Smart Cards) detection of an “event” and processing (classification, recognition, analyzing) the event (ASOC) with RF response of the result Ref: B.W. Cook et al, “SOC Issues for RF Smart Dust,” Proc IEEE June 2006

5. soc 8.5 Untethered systems: RFID vs ASOC

6. soc 8.6 ASOC basics small size –basic die type: O (1/4 -1 cm 2 x ½ mm) –note, long term: could be printed on an ultra thin base power and energy, self contained persistent storage communications with environment (network) one or more types of sense and reaction

7. soc 8.7 Area, Time (Performance) and Power design tradeoffs Dynamic power only

8. soc 8.8 Area cost of processed silicon: $1-10/cm 2 most designs target –1 cm 2 or a little less in area; the sweet spot –gives 90%+ yield larger dies have –lower yields –fewer dies / wafer –costs can be 10x for a doubling of die size small dies aren’t much cheaper –limited by testing and packaging

9. soc 8.9 Silicon device density scaling Net: there’s either a 1 billion transistors or 100 Mega Bytes of Flash on a 1cm 2 die

10. soc 8.10 Power and batteries eliminating the external battery is the key technology for ASOC –no pins, distribution problems must print or deposit battery on reverse side of die can scavenge power –source may be unreliable –adds on die complexity

11. soc 8.11 Battery technology [2] The POWER FAB (Thin Film Lithium Ion Cell) battery system,. http://www.cymbet.com [1] PowerID, Power Paper Corp. www.powerpaper.com

12. soc 8.12 Scavenging Energy [YEA] E.M. Yeatman, “Advances in power sources for wireless sensor nodes,” Proceedings of 1st International Workshop on Body Sensor Networks, London, 2004 [SOD] Sodano et al, ” Electric power harvesting using piezoelectric materials,” 10th SPIE Conference on Smart Structures and Materials, 2003

13. soc 8.13 Energy capacity at 1  w usage Net: an on die battery will have only 10 Joules unless energy is scavenged. At a 10% duty cycle this gives better than a 3 year lifetime.

14. soc 8.14 Power and performance with a power budget of 1  w how to provide meaningful performance? if today’s processor offers 5 GHz at 100w –by the cubic rule 1  w (dynamic power) should offer 10.5 MHz: (10 -8 ) 1/3 = 2.1 x 10 -3 but with lots of transistors we need to use them to recover performance

15. soc 8.15 Power and performance with a power budget of 1  w how to provide meaningful performance? static power is also a big issue –must be of the O (0.1)  w methods to reduce static power consumption –sub threshold circuits –power islands –sleep transistors –SOIAS: Silicon on Insulator Active Substrate

16. soc 8.16 Performance with low clock rate No clock: asynchronous logic –no unnecessary state transitions Minimum or no cache system –backed by compatible Flash VLIW and specialized multi processors –to recover performance

17. soc 8.17 The ASOC die

18. soc 8.18 Networking: it’s the ensemble that produces the action no individual die is expected to produce a recognition or a definitive action recognitions are passed to neighbors; can be sent to higher level for action or through swarm computing arrived at via the network current software models are inadequate in this regard for hardware, communication is the key

19. soc 8.19 Untethered inter die communications Light or RF modulated light can be low power –relatively easy to focus/ defocus –free space signals are non interfering –but, must have line of sight RF, components well understood –RFID technology –can require power; especially at high frequency –antenna focuses power based on carrier frequency

20. soc 8.20 On die lasers for communications It’s possible to achieve 100 Mbps with 1  watt without noise But: ambient light is noise; need 10x signal over noise; also distance requires optics to collimate the beam for low divergence

21. soc 8.21 RF, smart dust:10 11 bits/Joule/ Meter. Ref: [Coo] B. W. Cook et al, “SOC Issues for RF Smart Dust,” Proc IEEE June 2006 65x30x25 mm Prototype; Target 2 mm 3

22. soc 8.22 Today’s ASOC; implantable RF 5 mw (peak), 2 meters, 1 Mbps Ref: Zarlink’s medical implantable RF

23. soc 8.23 Audio sensors time or frequency domain ear uses frequency domain need sensitive chip mounted crystal transducers –to provide signal (voltage) to sensor

24. soc 8.24 Audio sensors: Cochlear implant Ref: Wikipedia Speech processor, Transmitter Receiver, electrodes RFRF

25. soc 8.25 Audio sensors; cochlear chip; series of frequency bandpass filters Ref: B. Wen et al “Active Bidirectional Coupling in a Cochlear Chip” Advances in Neural Information Processing Systems 17, Sholkopf Ed., MIT Press, 2006

26. soc 8.26 Vision and recognition: edges Ref: T. Komuro, “SIMD Processor for Vision“ IEEE JSSC, VOL. 39, NO. 1, JAN 2004 64x64 pixel array (PEs) with reconfiguration; PE chaining and fast summation for edge detection

27. soc 8.27 Vision and recognition: templates Ref:Etienne-Cummings, “A Vision Chip for Color Segmentation and Pattern Matching,” EURASIP Journal on Applied Signal Processing 2003:7, 703–712 Object recognition with color (RGB to HIS) 128 x 64 pixel element array Uses SAD array scan to match against 32 Templates (432 b each) Achieves 30 frames per second with 1 mw

28. soc 8.28 Movement: 2D ASOC die is 10x10x0.6mm and weights about 200 mg with 1 Joule of energy (10 7 ergs); lifting 200mg 1 cm requires 20 ergs or 2  w-sec so as long as speed is slow (order of cm / sec) or duty cycle is low, simple motion using nano motors shouldn’t be a problem

29. soc 8.29 Movement: Flight Toward 30-gram Autonomous Indoor Aircraft: Vision-based Obstacle Avoidance and Altitude Control J. Zufferey and D. Floreano,” Toward 30-gram Autonomous Indoor Aircraft: Vision-based… Control,” Laboratory of Intelligent Systems, EPFL http://www.youtube.com/watch?v=Lv6amv0yDIg

30. soc 8.30 Movement: flight J. Zufferey and D. Floreano,” Toward 30-gram Autonomous Indoor Aircraft: Vision-based … Control,” Laboratory of Intelligent Systems, EPFL

31. soc 8.31 Movement: the fruit fly Drosophila melanogaster

32. soc 8.32 Fruit fly length 2.5 mm; volume 2 mm 3 0.65 milligram; 1 month lifetime vision: 800 units each w 8 photoreceptors for colors thru the UV (200k neurons); 10x better than human in temporal vision also olfaction, audition, learning/memory flight: wings beat 210x /sec; move 10 cm/sec; rotate 90 0 in 50 ms

33. soc 8.33 Summary: ASOC the goal is to create a catalog of techniques, sensors, controllers, transceivers and processors together with an interconnection and design methodology for application ASOC ASOC can be one or many die; external units as required by system we’re a long way in Cost-Time-Power from a fruit fly; but we’re making progress!

34. soc 8.34 Future (2): self-optimise/self-verify 2005 International Technology Roadmap for Semiconductors: overall design challenges –cost-driven design optimisation –verification and test –re-use approach to address all 3 challenges? –key elements –challenges –summary

35. soc 8.35 Approach: key elements optimise and verify: hardware + software –meet requirements efficiently and demonstrably self-optimising and self-verifying design (SOSV) –preserve property in design composition self? –aware of context –capable of planning –effective external control 2 stages –pre-deployment: building design, compile time –post-deployment: operational, run time

36. soc 8.36 ----------------------------------------------------------------------------------- Pre-deployment Post-deployment ----------------------------------------------------------------------------------- focus designer productivity design efficiency aim optimize/verify initial optimize according to post-deployment design situation context design tool environment, operation environment, often static often dynamic acquire context from parameters affecting from data input tool performance e.g. sensors planning plan post-deployment plan to meet post- optimise/verify deployment goals external control frequent infrequent ----------------------------------------------------------------------------------- Pre- and post-deployment

37. soc 8.37 Re-use high-level generic design –requirements + context: multiple designs –optimise: options + parameters + abstraction levels facilitate design composition –preserve self-optimising and self-verifying –modularity of building blocks + interfaces platform-based evolution –re-use un-verified design: risky –automate re-verification after changes –platform for re-use: from automatic to self

38. soc 8.38 Pre-deployment: overview available computing resources –components + pre-context: locate and tune tools –current context: optimise resource + error recovery designer –adapt components: requirements + post-context –choose control: automation of search strategies –decide: re-use or re-invent challenges –productive interaction: designer + tools –avoid combinatorial explosion –maximise re-use: incremental design

39. soc 8.39 Pre-deployment: example of choices circuit technology: eg ASIC or FPGA input/output: options memory: hierarchy + options interconnect: e.g. bus, switch, network-on-chip granularity: configurable unit, custom instruction synchronisation: e.g. clock domains, self-timed parallelism: processors, hardware/software data representation optimisation post-deployment optimisation/verification

40. soc 8.40 Example: number of processors From: Fidjeland & Luk 05

41. soc 8.41 Post-deployment: situation-specific optimization and verification opportunities –design upgrade –run-time conditions, e.g. noise, process variation –program phase optimisation optimisation and verification process –light-weight: on-site, e.g. proof-carrying code –heavy-weight: remotely, verified by signature run-time system –deals with exceptions –error diagnosis facilities

42. soc 8.42 Example: program phase optimisation From: Styles and Luk 05 program phase: working set remains constant reconfigure to speed up frequent branches

43. soc 8.43 Autonomous systems control strategy –make decisions to optimise itself –model of world: planning and action –understand trade-offs: e.g. reconfigure or not event-driven just-in-time reconfiguration –component meta-data description –assemble + tune partially-optimised components –hide reconfiguration latency other possibilities –machine learning –self-organising feature map

44. soc 8.44 Example: dynamic power optimisation power surge while self-optimising/verifying

45. soc 8.45 Challenges: theory + practice for: productive automate: evolutionary vs disruptive SOSV design: specify + analyse requirements composable description: design + context multi-level capture: domain-specific constraints open standard: design, optim/verify programs

46. soc 8.46 Summary self * (optimising+verifying) = trusted re-use –unify: autonomic, self-test, dynamic optim., RTR –better design + more productive self-optimising self-verifying design platform –FPGA-based systems: large + small –autonomous system-on-chip + network of ASOCs –applications: ubiquitous, dependable, secure, robust new generation of designers –building blocks + tools: made smarter –specify, analyse, adapt: requirements + search