1. Sebastian Schopferer University of Freiburg IEEE RT 2010, Lisboa Development and Performance Verification of the GANDALF High-Resolution Transient Recorder System

2. 27 May 2010Sebastian Schopferer, RT 2010, Lisboa2/18 COMPASS – Fixed Target Experiment COMPASS – Experiment: 240 physicists from 11 countries and 28 institutions

3. 27 May 2010Sebastian Schopferer, RT 2010, Lisboa3/18 COMPASS Facility (since 2002) 50m Hadron Spectroscopy, Deep Inelastic Scattering μ 190 GeV/c high intensity (2∙10 7 s -1 ) large halo  polarized target (NH 3 or LiD)  2-stage spectrometer  several types of trackers  calorimeters (ECAL, HCAL)  PID (Muon-Filters, RICH) ,K

4. 27 May 2010Sebastian Schopferer, RT 2010, Lisboa4/18 COMPASS-II Upgrade 2,5m liquid hydrogen target COMPASS spectrometer: trackers, calorimeters, PID p  μ μ Recoil Proton Detector: to ensure exclusivity of the observed process DVCS:  p   p  COMPASS-II proposal: determination of Generalized Parton Distributions

5. 27 May 2010Sebastian Schopferer, RT 2010, Lisboa5/18 Recoil Proton Detector (RPD) 4m -4V measurement of: -time-of-flight (σ < 200ps) -energy deposit high luminosity: separation of pile-up pulses is required p inner barrel (A): Ø 0.50 m outer barrel (B): Ø 2.20 m μ  0V 0ns40ns

6. 27 May 2010Sebastian Schopferer, RT 2010, Lisboa6/18 VME64x Interface USB 2.0 S-Link Interface to DAQ S-Link Interface to DAQ VITA 41.0 VXS Interface VITA 41.0 VXS Interface TCS 8 Analog Inputs 8 Analog Inputs 8 Analog Inputs 8 Analog Inputs 144Mbit QDRII+ 4Gbit DDR2 Memories 144Mbit QDRII+ 4Gbit DDR2 Memories V5 LXT FPGA for Memory Control & Data Output V5 LXT FPGA for Memory Control & Data Output 500Mhz Bandwidth Analog Inputs 500Mhz Bandwidth Analog Inputs V5 SXT FPGA for Data Processing V5 SXT FPGA for Data Processing 12 bit 500MS/s ADCs 12 bit 500MS/s ADCs 16bit DACs for Offset Correction 16bit DACs for Offset Correction Digital Pulse Processing for real-time extraction of time, amplitude and integral information

7. 27 May 2010Sebastian Schopferer, RT 2010, Lisboa7/18 ADC Mezzanine Card 8 ADC channels (12bit@500MS/s or 14bit@400MS/s) optional time-interleaved mode offsets are adjustable by DACs gain is adjustable by changing some passive components flexible input range (e.g. -4V..0V, -1V..0V, -2V..+2V, …)

8. 27 May 2010Sebastian Schopferer, RT 2010, Lisboa8/18 Time Interleaved Mode Advantage: High Resolution @ High Sampling Rate 12bit @ 1Gsps Challenges –Symmetric clock distribution –Clock Jitter < 1ps –Symmetric placement of devices FPGA Analog IN DSPLL Clock System 38.88MHz Exp. Clock 500MHz 0° 500MHz 180° AI ADC Time Analog Digital Time Possible errors are corrected –Gain error –Offset error

9. 27 May 2010Sebastian Schopferer, RT 2010, Lisboa9/18 Sampling Clock Requirements Jitter of sampling clock increases noise on signal and reduces Effective Number of Bits High Precision Clock Source needed! ENOB = (SNR – 1.76) / 6.02

10. 27 May 2010Sebastian Schopferer, RT 2010, Lisboa10/18 Sampling Clock Quality AnalogIN LMH6552 ADC Clock Synth TCS Receiver 155,52MHz 505.44MHz Si5326 ADS5463 AnalogIN LMH6552 ADC Clock Synth OCXO 500MHz 20MHz Si5326 ADS5463 Sampling JitterTCS Jitter nsps 900 fs Sampling JitterOCXO Jitter nsps 730 fs

11. 27 May 2010Sebastian Schopferer, RT 2010, Lisboa11/18 GANDALF Performance Signal-to-Noise Ratio (Effective Number of Bits) f in LMH6552 ADC Measurement Setup: AFG3252 and high performance band-pass filters

12. 27 May 2010Sebastian Schopferer, RT 2010, Lisboa12/18 Fit Algorithms for Time Extraction Digital Constant Fraction Discrimination Delay Fraction factor t meas.

13. 27 May 2010Sebastian Schopferer, RT 2010, Lisboa13/18 GANDALF dCFD Performance create PMT-like pulses with function generator pile-up pulses with amplitude and phase modulation timing resolution vs. pulse amplitude sampled in 1GS/s mode 4V40mV

14. 27 May 2010Sebastian Schopferer, RT 2010, Lisboa14/18 GANDALF Laser Test PMT: RT1450 1.1 – 1.3kV Laser Pulser GAN DALF sampled in 1GS/s mode

15. 27 May 2010Sebastian Schopferer, RT 2010, Lisboa15/18 Fast Recoil Detector Trigger Trigger Processor GANDALF Proton Trigger VXS Backplane Analog Inputs Exp. Trigger i target inner Layer outer Layer A i+1 AiAi A i-1 B i+1 B i-1 t proton - t muon energy deposit vs.  geometric structure μ p B A  VITA 41.0 Specification

16. 27 May 2010Sebastian Schopferer, RT 2010, Lisboa16/18 GANDALF as TDC & Logic Module Trigger & Clock Data Processing, Analog Trigger Generation Memory Controller VME Interface, Board Config. Compact Flash Memory 16 HS Channels via VXS to Switch To Backplane To Transition VME64x Interface to VME CPU QDRII 144Mb DDR2 4Gb HF CLK S-Link Interface via P2 USB TCS 64 channel LVDS/LVPECL inputs 1 NIM Input 2 NIM Outputs 64 channel LVDS/LVPECL inputs 1 NIM Input 2 NIM Outputs 32 ch. LVDS input NIM I/O (LEMO) 32 ch. LVDS input NIM I/O (LEMO) Implementation of TDCs, scalers, mean-timers, … inside the FPGA

17. 27 May 2010Sebastian Schopferer, RT 2010, Lisboa17/18 GANDALF Mean-Timer 64 mean timer channels max. time difference: 29 ns resolution: 230 ps variable input delay (max 8ns) to compensate cable lengths mean-timer signals are fed into coincidence matrix matrix pixels can be switched on/off on-the-fly (John Bieling, University of Bonn)

18. 27 May 2010Sebastian Schopferer, RT 2010, Lisboa18/18 Generic Advanced Numerical Device for Analog and Logic Functions … is a VME64x readout system for high energy physics … is a transient recorder which meets all design goals: –Effective Number of Bits > 10 bit –Time resolution < 50 ps … is a logic module with possibilities to implement TDC, Scaler, mean-timer and trigger matrix functionalities … is a VXS payload board to allow multi- module trigger decisions

19. 27 May 2010Sebastian Schopferer, RT 2010, Lisboa19/18 Thanks for your attention!

20. 27 May 2010Sebastian Schopferer, RT 2010, Lisboa20/18 Backup

21. 27 May 2010Sebastian Schopferer, RT 2010, Lisboa21/18 Timing Resolution Methods converge at low amplitudes Spline algorithm reaches better timing resolution Constant Fraction reaches good timing resolution with very low calculation efforts! Timing Resolution

22. 27 May 2010Sebastian Schopferer, RT 2010, Lisboa22/18 Near following Pulses Best achievable resolution for near following pulses Digital signal process developed for double risetime range

23. 27 May 2010Sebastian Schopferer, RT 2010, Lisboa23/18 GANDALF Performance II 1GHz sampling rate Offset correction by DAC Gain correction by FPGA 1GHz sampling rate Offset correction by DAC Gain correction by FPGA Gain Adjustment 10bit ENOB Interleaved:

24. 27 May 2010Sebastian Schopferer, RT 2010, Lisboa24/18 FPGA TDC Implementation Shifted Clock Sampling

25. 27 May 2010Sebastian Schopferer, RT 2010, Lisboa25/18 Share FPGA Resources Constant Fraction

26. 27 May 2010Sebastian Schopferer, RT 2010, Lisboa26/18 8 Channel AD Conversion @ 500Msps 12bit 16bit offset DAC Trigger & Clock 8 Channel AD Conversion @ 500Msps 12bit 16bit offset DAC 8 Analog Inputs USB TCS Data Processing Online Feature Extraction Memory Controller VME Interface, Board Config. Compact Flash Memory low latency connection via VXS to Trigger Processor To Backplane To Transition VME64x Interface QDRII 144Mb DDR2 4Gb HF CLK Readout via CERN S-Link Interface 8 Analog Inputs To Backplane

27. 27 May 2010Sebastian Schopferer, RT 2010, Lisboa27/18 Data Bus to GANDALF Board Digital Mezzanine Card NIM I/O (LEMO) TTL to NIM Buffer High Density Connector 32 ch. LVDS input LVDS Buffer LVDS Buffer LVDS Buffer LVDS Buffer LVDS Buffer LVDS Buffer LVDS Buffer LVDS Buffer LVDS Buffer LVDS Buffer LVDS Buffer LVDS Buffer LVDS Buffer LVDS Buffer LVDS Buffer LVDS Buffer LVDS Buffer LVDS Buffer LVDS Buffer LVDS Buffer LVDS Buffer LVDS Buffer LVDS Buffer LVDS Buffer NIM to TTL Buffer

28. 27 May 2010Sebastian Schopferer, RT 2010, Lisboa28/18 Messungen zur Zeitauflösung JitterTCSSi5326 TIE130ps16ps Board vs Board 90ps5ps Differenz der TIEs zwischen 2 GANDALF Boards: 5ps Zeit 2,5μs / div TIE 10ps / div Exp. Clock FAN OUT GANDALF

29. 27 May 2010Sebastian Schopferer, RT 2010, Lisboa29/18 Transient Recorder Challenges –Define and calculate the time of the signal shape –Time of Flight calculation with a resolution of < 200ps –Determine the amplitude of the signals with high dynamic range –Seperate signals from pile-up pulses –Create a trigger for recoil protons from multiple signal channels