1. ADF4193 Low Phase Noise, Fast Settling PLL Frequency Synthesizer

2. By Mike Keaveney, Patrick Walsh, Mike Tuthill, Colin Lyden, Bill Hunt
BASED ON A 10ms Fast Switching PLL Synthesizer for a GSM/EDGE Base-Station By
Mike Keaveney, Patrick Walsh,
Mike Tuthill, Colin Lyden, Bill Hunt
ISSCC 2004 / SESSION 10 / CELLULAR SYSTEMS AND BUILDING BLOCKS / 10.6

3. FUNCTIONAL BLOCK DIAGRAM

4. No connection here
50Ω
52Ω

5. FEATURES APPLICATIONS New fast settling fractional-N PLL architecture
Single PLL replaces ping-pong synthesizers
0.5 degree RMS phase error at 2 GHz RF output
Digitally programmable output phase
RF input range up to 3.5 GHz
3-wire serial interface
On-chip low noise differential amplifier
Phase noise figure of merit –216 dBc/Hz
Loop filter design possible using ADI SimPLL
APPLICATIONS
GSM/EDGE base stations
PHS base stations
Instrumentation and test equipment

6. Background – GSM Base-station Synthesizer Requirements
547ms
30ms f2 f1 f3
PA o/p power
~10ms for Tx Synth. to switch
Slide 2 (2 mins.)
A GSM Base-station imposes conflicting requirements on the synthesizer; it must have low phase noise and spurious during the data burst, which calls for a narrow PLL loop bandwidth. But it must also be agile enough to frequency hop over the entire band in less than 10us... this calls for a wide loop bandwidth.
To date this can only be done with two narrow bandwidth PLLs in a ping-pong arrangement; where one PLL spends the full timeslot locking to the next channel while the other is active.
The ping-pong is expensive as it requires two PLL chips and two high performance VCOs and must provide over 90dBs of isolation, between the two, at RF frequencies up to 2GHz.
In this paper a fast locking synthesizer is proposed that can meet the conflicting requirements of fast hopping and low phase noise with a single PLL, which results in greatly reduced cost and complexity for the base-station system designer.
Referring to the GSM timeslot diagram, it can be seen while a receive synthesizer may utilise the full 30us guard period to frequency hop, the transmit synthesizer has a much more demanding lock time requirement.
To ensure that the transmitter stays within the GSM "spectrum due to switching" mask, the transmit synthesizer cannot change frequency until the Power Amplifier has ramped down. And, once it does switch, the synthesizer must be locked at the new frequency before the PA starts to ramp up again. Allowing time for the carefully controlled ramp profiles for the PA, this leaves just 10us for the transmit synthesizer to frequency hop.
However it does not need to meet the phase noise and spurious specs until the start of the active part of the burst, which is 10us later.
This indicates that a dual bandwidth PLL scheme could be feasible where a wide bandwidth mode is used for fast frequency locking which then reverts back to narrow BW mode while the PA is ramping up, in time for the start of the active part of the burst.
Switch frequency in 10ms => Wide PLL BW
Low Phase Noise during Data Burst
Low Spurious during Data Burst
} => Narrow PLL BW

7. Phase Noise & Lock Time Simulations
320kHz BW:
Lock Time: 6.3ms
5 ms/div.
1805
1880 5 10 15
-50 50
40kHz Loop BW:
Lock Time: 120ms
No cycle slip if
BW>0.8*Fstep/2pN
[Cicero JSSC’00]
Phase
(Deg.)
Frequency
(MHz)
50 ms/div.
100
150
Phase Noise
(dBc/Hz)
1kHz
1MHz
-140
-100
Slide 3 (1 min.)
In this slide we explore the trade-offs between phase noise and lock time.
The phase noise simulation results at the top of the slide are with a fractional-N PLL with 26MHz reference and a 1800MHz output frequency. Also shown is the phase noise mask for a transmit synthesizer.
We can see that 40kHz is about as wide as we can go before breaking this mask.
* However, we can see (from the settling time plots on the bottom left), that with a 40kHz band-width, a 75MHz jump across the full DCS-1800 TX band, takes 120us to settle to within 5 degrees of final phase.
Five degrees of final phase is the locking requirement for EDGE.
Increasing the bandwidth by 8x, to 320kHz, fails the mask but reduces the lock time to just over 6us.
With such a fast loop, the error at the phase detector never exceeds 2 pi, so the PFD does not cycle slip... leading to an almost 20x improvement in lock time for just an 8x increase in BW.
N=1880/104
0.8*75M/(2pN)=528k

8. 8x Bandwidth Switching N CP CZ R/8 7R/8 Fout Fref 8f0 f0 64x ICP
Charge Pump
Cell Array,
ICP<63..0> CP CZ
R/8
7R/8
Fout
PFD
Fref
0dB
36dB
-180o
-135o
8f0 f0
64x ICP
1x ICP
Slide 4 (1 min.)
A common approach to widening the PLL bandwidth is to increase the charge pump current and at the same time switch the loop filter “zero” resistor.
Since the loop gain rolls off at 40dBs per decade or 12dBs per octave, 64x increase in charge pump current is needed to increase the loop bandwidth by 8x.
This is easily implemented using, for example, an array of 64 identical charge pump units.
The phase margin can be maintained at 45-degees for optimum settling, if the resistor that determines both the pole and zero frequencies is reduced in value by 8x, while the current is at 64x.
While this scheme has been known for 25 odd years, practical implementations of it to date have not realised it's full potential for lock time improvement. This is because the loop settles slowly from the phase disturbance that occurs when switching back to narrow band mode.
In this paper we describe several techniques that ensure that this disturbance is no greater than the +/- 5-degree limits that are acceptable for EDGE, thus allowing us to fully take advantage of the wide BW mode.
Wide BW: x ICP & R/8
Narrow BW: 1x ICP & R
[Ref: Crowley ‘78]

9. PLL Static Phase Error t  DICP t Matched Mismatched Fref Fdiv UP DOWN
Dt  ICP
t  DICP
+ICP
Charge
Balance:
-ICP t Dt
Slide 5 (1 min.)
The mechanism that causes the largest phase disturbance is the change in the static phase error that the PLL settles to, in wideband versus narrow band modes.
The diagram on the left shows the case when there is perfect matching in the charge pump’s up and down currents. Since these cancel each other out exactly, the loop locks with zero static phase error between the PFD inputs.
When there is mismatch between the up and down currents, as shown in the diagram to the right, the PLL will now lock with enough static phase error between the PFD inputs to restore the balance of charge in the loop filter, over a reference cycle. This static phase offset is not a problem in the base-station application…. as long as it does not change by more than 5 degrees, during the active part of the burst.
As shown in the example, with a 3ns minimum pulse width for good phase detector linearity, as little as a 0.25% change in charge pump mismatch will give rise to a 7ps skew between the PFD inputs. While this is just a fraction of a degree at the PFD reference frequency, a change of 7ps at the detector corresponds to a 5-degree phase change at a 1.8 gig output frequency.
At Balance: Dt  ICP = t  DICP
1.85GHz  7.5ps ( 26MHz)
With t = 3ns, for Dt < 7.5ps, requires ICP mismatch < 0.25%

10. Conventional Charge Pump PLL
PFD
ICP<63..0> UP DN
ICP Envelope
64x 1x
200°/
div.
Output Phase (simulation)
Slide 5b (1 min.)
In a conventional charge pump PLL, up current is generated from a PMOS current source and down current from an NMOS.
Because these are different device types and are manufactured at different times, the up to down matching may be no better than 10 %.
The phase settling plots show the result of two lock time simulations. In one there is perfect matching at both 64x and 1x. In the other, the 1x cell has a 10% mismatch.
In this case, when the charge pump current is reduced from 64x to 1x, there is a 10% delta in the mismatch. This causes a 200 degree phase step at the output, consistent with the model shown in the previous slide. And now, because the loop bandwidth is narrow, this phase step takes about 50us to settle back to within 5 degrees of it’s final value.
In the ideal case, because the phase disturbance due to bandwidth switching is < 5 degrees, the lock time is whatever value was achieved in wide bandwidth mode.
In order to achieve this, an architecture is needed that ensures that the change in mismatch from 64x to 1x, remains less that 0.25 %.
The strategy we have adopted is to minimise the mismatch at both 64x and 1x currents and hence by definition any change in mismatch will be minimised.
While this mismatch delta is the primary mechanism, dynamic effects such as timing mismatch, charge injection as well as leakage currents are all mechanisms that cause phase steps at the output. These will also need to be catered for with the new architecture.
64x → 1x ICP
mismatch D = 10%
 Df = 200°
Ideal
Time (5ms / div.)

11. Differential Charge Pump Concept
Better Up/Down Matching
Same Type Devices
Symmetric Layout
Charge Injection is Common Mode to Vtune
Requires
Low Noise Diff-amp
CMFB
Matching improved but still residual mismatch due to process ( ~= 0.5%)
mp1
mp2
Vbias1
Vtune
DNp
UPp
+ –
CPO+
CPO–
DNn
UPn
Slide 6 (1.5 min.)
A fully differential charge pump architecture offers the best possible up to down matching.
To pump up, current from mp1 is sourced out through CPO+ and sinks through CPO- into mn2. This causes the differential output voltage to increase. The pump down operation, indicated in blue, is a mirror image of this.
The Up to Down mismatch problem is reduced by at least an order of magnitude as it now depends on how a PMOS matches a PMOS and an NMOS matches an NMOS.
Also thanks to the differential structure, the charge pump outputs each only need to swing over half the required tuning range. This compliance voltage relaxation greatly eases the design constraints on the charge pump.
Another advantage is that the charge injection in the switches is now common mode to the tuning voltage, which eases another difficult problem.
However, all these advantages are not without some disadvantages.
The biggest of these is that now a low noise, differential to single-ended amplifier is required to generate a single ended tuning voltage for the VCO.
Also, since the PLL only cares about the charge pump’s differential output voltage, a common mode feedback loop is required to bias the outputs at an appropriate common mode level.
Finally, while mismatch is reduced considerably with the differential architecture, and is ideally zero, there will still be a residual mismatch due to process variations in threshold voltage and poly line width. Leakage, headroom and die area set a limit on how much these variances can be reduced and a realistic expectation is that of a mismatch sigma of around 0.5%.
Therefore, the differential architecture on it’s own it’s still not good enough to guarantee the 5 degree settling spec.
Vbias2
mn1
mn2

12. Charge Pump Cell with Chopped Outputs5V
mp1
mp2
Vbias1
UPp1
DNp2
UPp2
DNp1
~2V
CPO+
CPOB–
~2V
DNn1
UPn2
DNn2
UPn1
Vbias2
Slide 7 (1.5 min.)
However, this residual mismatch due to process variation can be dynamically eliminated by chopping the Up and Down currents.
The fully differential structure, with identical up and down sections, makes this possible.
The basic charge pump structure is similar to other differential charge pump architectures using the current steering technique. During the off period of the PFD, the PMOS, as well as NMOS currents are steered to a low impedance bias voltage, of around 2V.
Gating logic on the up and down signals from the PFD controls the switches to implement the chopping scheme where the up and down current sources are alternated from left to right on every reference cycle. The switches that alternate the pump up current source from left to right are highlighted in red and green, according to chopping phases 1 and 2.
Since the mismatch error is chopped at half the PFD reference frequency, this leads to spur at 13MHz. While this spur is well attenuated by the 40kHz loop, it could mix sigma-delta quantisation noise around Fref/2 to base-band…. where it could degrade the in-band phase noise of the synthesizer. Hence a lot of care was taken in the design and layout of the cell to ensure that all systematic sources of mismatch were eliminated, in order to keep the amount of error being chopped, small.
Charge injection in the switches, and output current variation versus output voltage, can result in second order mismatch effects, that are not cancelled out with chopping.
To counter this, cascode devices, (which are not shown in this simplified schematic), are used on the switches to minimise variation in response time and charge injection, versus output voltage. Additional cascodes, (again not shown for simplicity), are used on the current sources to increase their output impedance for minimal up to down current variation over the desired charge pump output voltage range.
mn1
mn2
f1 , f2
Fref
UP1,DN1
UP2,DN2

13. Chopped Up/Down Signal Paths from PFD
Fref
UP1, DN2 D Q f2 RB t RB f2 D Q
Fdiv
DN1, UP2 f1 f1 f2
Slide 8 (0.5 min) (~14 left)
Timing or pulse width mismatch between the up and down paths has a similar effect on phase offset as up to down current mismatch.
Since as little as 7ps can cause 5 degrees as the output, gate delay mismatch between the up and down signal paths, can become significant.
By chopping the complete up and down paths from the inputs of the PFD to the outputs of the charge pump, this effect is eliminated.
Again care was taken to ensure full symmetry in the layout of the up and down signal paths so that the error being chopped is as small as possible and thus have minimal detrimental effect on in-band phase noise.
Fref
Fdiv
Chopped Output Charge

14. Diff-Amp CPO – Vout 10000.5 Vref 10000.5 CPO + Phase Noise
500
500
Vout
10000.5 – +
Vref
10000.5
CPO +
500
500
5mA
5mA
-130
-100
Phase Noise
40kHz
Slide 9 (1.5 min)
A low noise, differential to single-ended amplifier is needed to convert the differential charge pump output signal into a single ended control voltage for the VCO.
DC accuracy and 1/f noise are not major concerns in the design of the diff-amp as these are both suppressed by the PLL.
Input current mismatch would be a problem though as the loop would react to it by introducing a static phase offset. When the charge pump current is reduced, the phase offset would increase accordingly, resulting in a step change in the output phase, the transient of which would be slow to settle out in narrow BW mode.
Hence the input buffers are PMOS source followers for zero input current and therefore zero input current mismatch. They are sized large enough to ensure their 1/f noise is sufficiently low to be suppressed by the loop gain.
They are followed by NPN emitter followers for level shift and low output impedance.
The op-amp is an NPN-input, single stage, folded cascode design for low noise and fast settling.
Output noise from the amplifier, above the 40kHz loop bandwidth, FM modulates the VCO.
Here the noise is dominated by the op-amp’s input diff-pair and thermal noise from the 500 ohm resistors. The 500 ohm value was chosen for the best compromise between low noise and reasonable power consumption. An output noise density of 7nV per root Hz from 100kHz upwards, ensures that the far out phase noise, measured at the VCO, remains within spec.
PLL suppresses DC errors & 1/f noise.
Want zero IIN mismatch  MOS i/p’s
Noise > 40kHz → FM sidebands
 < 7nV/Hz Vout

15. Common Mode Feedback Loop
CPO+
CPO–
UPp
DNp
UPn
DNn UP DN + –
~2V
200mA
Charge
Pump _
PFD UP DN
Slide 10 (1 min)
Because the PLL is only concerned with the charge pump’s differential output voltage, a common mode feedback loop is needed to bias the charge pump outputs at an appropriate common mode level,
The charge pump output common mode level is sensed and compared to a reference at approximately 2V, which is around the optimum bias point for the charge pump.
The feedback signal modulates a current that is used to delay the trailing edge of the pulses from the PFD to the PMOS versus NMOS current switches in the charge pump.
Wider PMOS current pulses will increase the common mode level and wider NMOS pulses will decrease the level.
The leading edge of the UP and DOWN, active low signals is controlled by the PFD and is not interfered with by the pulse stretch circuit, so that low phase noise is preserved.
The pulse stretch circuit is basically a string of two inverters which outputs a fast leading edge and a current controlled trailing edge. The same control current is mirrored to both up and down pulses.
Since both the up and down trailing edges are adjusted together and by the same amount, the common mode feedback loop acts independently of the PLL.
Pulse Stretch circuit
→ Fast leading edge, current controlled trailing edge
→ Control current mirrored to both up and down pulses.

16. CMFB Pulse Stretch SignalsUP
} from PFD DN
UPp
} to PMOS switches
DNp
} to NMOS switches
UPn
DNn
Phase info
from PFD
remains intact
Slide 10b (1 min.)
This timing diagram in this slide illustrates this operation.
In this example, the common mode feedback loop acts to increase the output common level. It does so by widening the Up & Down pulses to the PMOS switches and reducing the width of the NMOS pulses. Hence there is a net increase in charge, shown here in green, out to the loop filter.
While all this is going on, notice that the phase info, imposed by the PFD, on the up and down leading edges remains intact.
Hence the common mode feedback loop acts independently of the phase locked loop, and because noise from it’s circuitry is common mode to the PFD, it has little impact on output phase noise.
Since the common mode signal is the same on both charge pump outputs, it also works seamlessly with chopping.
Differential CP output
Common Mode output

17. Proposed Fast Locking PLL
Fref
Fout D
Charge
Pump
<64:1>
Mod-130 SD
2C1
R2/16
2C2
7R2/16
÷ N / N+1
Fast Lock
Control + – C3 R3
External
R3/7 f1 f2
Slide 11 (1.5 mins)
This is a block diagram of the fast locking PLL, with the CMFB loop excluded for simplicity.
The VCO and loop filter components are external to the chip and are chosen to suit the particular transmit or receive band. The filter components are easily derived from the single ended case by doubling the capacitors and halving the resistor values.
This dual loop filter topology is preferred over a fully differential scheme, as the R2 resistor switches can be simple NMOS gates to GND and their charge injection is common mode to the VCO tuning voltage.
A transmission gate has to be used to switch the R3 resistor though. The PMOS and NMOS switches in this are sized to cancel the charge injection to a first order.
The charge pump is made up of 64 identical instances of the cell we saw earlier.
When a new frequency channel is programmed, the fast lock control logic closes the loop filter resistor switches and enables all 64 charge pump cells for the next reference cycle.
These stay enabled for a programmable number of timeout counter cycles, clocked by the reference. After the PLL has locked to the new frequency, the charge pump current is reduced and when it is at it's minimum, with just one cell active under the control of the PFD, the resistor switches are opened.
Open R2 & R3 switches when ICP 1x

18. ICP Reduction with SD Compensation
MUX 1 X2
Z-1 2 +
FRAC
SD Out – 3
130  16
ICP
(mA)
Fref 17 18
Time (µs)
Slide 12 (1 min.)
In the transition from wideband to narrow band modes, the charge pump current is reduced in 6 binary steps, with 4 reference cycles per step.
In a fractional-N PLL, the current pulses out of the charge pump have memory, imposed on their pulse widths by the sigma-delta modulator.
Because of this, if the charge pump current changes and the sigma-delta modulator does not know about it, then there will be a disturbance in the PLL that will be slow to settle out, when the bandwidth is reduced.
To ensure that it allows for the change, the state of the sigma-delta modulator is scaled one reference cycle ahead of each binary step reduction in charge pump current. This scaling involves doubling the contents of the second and third integrators in the 3rd order modulator.
The sigma-delta loop responds to this quickly, resulting in a 2x larger than normal output on the next cycle. This causes the PFD to generate a charge pump output pulse that is twice as wide, which compensates to a first order for the halving of the current.
So the slow PLL loop sees little overall change and meantime the fast sigma-delta loop has settled back to steady state within 1 or 2 clock cycles.
And now for some measurement results…

19. Measured: Phase Lock Time
75 MHz jump from 1880 to 1805 MHz
Time (ms)
Phase (Degrees)
Start
Slide 13 (1 min.) (8 left)
This plot shows the phase locking transient captured from a 75MHz frequency jump across the complete DCS-1800 transmit band.
The frequency is changed at time zero, and the PLL has locked, in wide BW mode within 10us.
When the bandwidth is reduced to 18us, the output phase noise noticeably reduces and the phase remains within +/- 5 degree window around it’s final average value…. which satisfies the requirement for EDGE.

20. Chopping Off vs. Chopping On
Time (ms)
Wide BW
Narrow
Phase (Degrees)
Chopping Off
Slide 14 (1 min)
This slide demonstrates the benefit of chopping.
The charge pump mismatch measured on this chip was close to zero with all 64 cells active and about 1% with the final one cell active…. so a change in mismatch of 1%.
With chopping disabled, the effect of this change can be seen in the 20 degree step in output phase that occurs when the PLL reverts to narrow BW mode. This causes the phase to fail the +/- 5 degree limits required for the active part of the burst.
In contrast, the same chip shows no noticeable step in phase between wideband and narrowband modes with chopping enabled, and the peak phase deviation, during the active part of the burst, remains inside the +/- 5-degree window.
Measured:
~1% ICP mismatch change  20° phase step w/o chopping

21. Measured: Output Phase Noise
DCS-1800 Tx LO Mask
dBc/Hz
Slide 15 (1 min.)
The phase noise plot is measured on a fractional channel at 1860MHz with a 26MHz PFD reference and chopping at 13MHz.
The spurs seen at low offset frequencies are harmonics of 50Hz from the power supply.
The integrated RMS phase error, measured from this single side-band phase noise plot, is 0.25 degrees.
The out of band noise falls within the mask for a Base-station’s TX Local Oscillator.
At low frequency offsets the noise is dominated by the input reference which is derived from a 104MHz REFIN signal divided on chip to 26MHz.
At frequency offsets between 1 and 10kHz the in-band phase noise approaches a floor of -100dBc/Hz.
From 40kHz upwards, noise from the diff-amp dominates, and beyond 400kHz it’s determined mainly by the external VCO.
RMS Phase Error (SSB) = 0.25°
Fout = 1860MHz, Fref = 26MHz, Fref/2
External VCO (Vari-L 1843T)

22. Measured: Spur Side-Band Levels
Slide 16 (1 min.)
This spur plot is measured at an output frequency of MHz which is 400kHz above an integer boundary of the 26MHz reference.
This is a worse case channel for spurs at 400kHz offset frequencies, which is an important corner frequency of the GSM mask.
The measured level of -75dBc meet the requirements.
Chopping is active at Fref/2 which would lead to a spur at 13MHz offset frequencies.
The mismatch error being chopped in this particular chip is 2%.
Even with this error, which is at the upper end of the expected distribution, the spur due to chopping is well below -95dBc and so is not a problem.
Fref/2, (with 2% measured ICP mismatch)

23. Die Photo Charge Pump Array N R SD Diff-Amp Lock Detect Loop Filter
Modulator N
PFD
Serial
Interface
Timers &
Control
Diff-Amp
CMFB
BGR R
Lock
Detect
Loop
Filter
Switches
Slide 18 (1 min)
Here is the Die photo.
The array of 64 charge pump cells takes up about a third of the active die area. It’s laid out in two blocks of 32 cells with outputs routed out the centre right of the die.
An additional cell is laid out in the middle of the bottom block of 32 with it’s transistors wired to make the diode devices used to bias the array.
In the PLL, the diff-amp is located after the loop filter and before the VCO. Hence it’s particularly sensitive to substrate noise pickup.
For this reason, the diff-amp block is laid out in the top right hand corner of the die, as far away as possible from the sigma-delta modulator and other digital logic.

24. Performance Summary Lock Time 10 ms RMS Phase Error 0.25 deg.
Idd: Charge Pump (5V)
33 mA
Diff-amp (5V)
30 mA
Remainder of chip (3V)
20 mA
Fractional Spurs (worse case at integer boundaries):
kHz
kHz
Spur due to Fref/2:
Reference Spur:
< MHz
< MHz
Chip Size
2.29 x 2.32 mm
Technology
0.35m BiCMOS w/ 5V options
Package
5x5mm 32 lead LFCSP
Slide 17 (2 mins.)
Here is a Summary of Measured Performance.
The PLL can frequency hop in 10us and still has an integrated phase noise of 0.25 degrees RMS.
The charge pump block takes 33mA off 5V supplies. The current steering architecture keeps IDD at the same level in both wide band and narrow band modes as a change in the IR drop in the power and ground tracks would give rise to a phase step at the output. We had no problem sacrificing supply current to prevent this, as power consumption is not a major issue in the base- station application.
Similarly the diff-amp burns 30mA to ensure that the out-of-band phase noise stays within spec.
The bulk of the remaining 20mA that’s consumed off 3V is taken by the CML N divider, followed by the sigma-delta modulator, which is clocked at 26MHz.
The worse case fractional spur levels occur in channels that are close to integer boundaries. These measured levels, at the important Mask offset frequencies of 400 and 600 kHz, are acceptable for a GSM base-station.
Far out spurs due to chopping and at the 26MHz reference frequency and it’s harmonics are all well below the -95dBc requirement.
The chip is approx 2.3 x 2.3 mm, is fabricated on a 0.35u BiCMOS process with thick oxide 5V devices, which are used in the charge pump and diff-amp blocks.
And lastly, the die is packaged in a 5 x 5 mm, 32 lead LFCSP chip scale package.

25. Summary
Static Phase Error due to Up to Down Mismatch in the PFD and Charge Pump blocks can be eliminated using a chopping scheme.
Loop Gain Changes during BW switching can be digitally compensated for in the SD Modulator.
A PLL based synthesizer can jump over the full TX band in <10ms and still meet the phase noise and spurious requirements for a GSM and EDGE base-station.
Slide 19 (1 min)
And finally, in summary… we have shown that…
Static Phase Error due to Up to Down Mis-match in the PFD and Charge Pump blocks can be eliminated using a chopping scheme.
Loop Gain Changes during BW switching can be digitally compensated for in the sigma-delta modulator.
A PLL based synthesizer can jump over the full TX band in <10us and still meet the phase noise and spurious requirements for a GSM and EDGE base-station.