1. Final Presentation Winter 2011-2012 Barak Shaashua Barak Straussman Supervisor: Idan Shmuel

2. Project Goals Implementation of a transmitter with Labview on FPGA. Project modulation types: 4 DQAM 8 DPSK

3. Hardware Connection 250MS/s 1.5MB/s 2.1GS/s 16MB memory Tabor – wx2182 as DAC NI FlexRio FPGA 7965R as TX NI 5761 Digitizer + NI FlexRio FPGA 7965R as RX

4. System Problems The bottleneck of the system is the speed of the DAC (Tabor wx2182) connection through the GPIB cable. Therefore, the system complexity was reduced by simulating The TX on the HOST. (Even though the TX works on the FPGA). Streaming is not supported by the DAC through the GPIB. Transmission is done in packets as big as the memory of the DAC. The DAC doesn’t transmit both channels synchronically (without trigger). As a result, the two channels are combined on the HOST and delivered to the DAC as one channel.

5. Data Rates Transmitter boundary: DAC max sample rate: 2.1GS/sec. In this rate carrier wave frequency: 1.05GHz. Receiver boundary: The ADC (NI5761) - max sample rate: 250MS/sec --> BW = 125MHz. Data boundary: Limited by the DAC memory size - 16M samples.

6. I Q Serial / Parallel Serial / Parallel Constellation Mapping Constellation Mapping DAC ISI Filter ISI Filter Up Converter Channel Coder Channel Coder Source Coder Combiner Sin(wt) + π/2 I Q DAC

7. Implementation Transmitter Acquisition Receiver

8. Transmitter - Symbol Mapping ***

9. Transmitter - Modulation

10. Transmitter - Data saving

11. Sending Data to DAC

12. Acquisition - FPGA

13. Acquisition - HOST

14. Symbol Decision Symbol Decision Constellation Mapping Constellation Mapping Channel Decoder RF Parallel / Serial ADC Sin(wt) + π/2 I Q I Q (+ Source) Timing & Carrier Recovery Timing & Carrier Recovery LPF

15. Transmission

16. Transmission Parameters We worked with Carrier frequency: 50MHz + 10 samples per period --> DAC operates in 500MS/sec. Symbol = 1 period of the carrier. Data rate: DQPSK - 2 bit/symbol - 100Mbit/sec. D8PSK - 3 bit/symbol - 150Mbit/sec. With 16M DAC memory - Data transition per transmission: 400KB (DQPSK) / 600KB (D8PSK).

17. Results 25MHz transmission --> BER=0 (One symbol error at the edge, not dependent on transmission length) 50MHz transmission --> BER=0 80MHz transmission --> BER=1/3 No alignment between samples and carried periods. Over sampling too low.

18. Summery In this project we acquired a lot of knowledge about communication and modulation. The project involved the integration of variety of systems and work environments. Future improvements: Labview - We found it hard to debug FPGA VI. Tabor - In our project setting, wx2182 wasn’t suitable.