1. This material exempt per Department of Commerce license exception TSU Xilinx On-Chip Debug

2. For Academic Use Only Chipscope 2 Debug and Verification is Critical Debug and verification can account for over 40% of an FPGA design time Serial nature of debug and verification can make it difficult to optimize Inefficient strategy may result in product launch delay – Loss in market share – Loss of first-to-market advantages Final Device DesignImplementation DesignSpecification 40%ofDesignTime Design Verification and Debug

3. For Academic Use Only Chipscope 3 Traditional Debug Challenges Limited Internal Visibility – How do I access the embedded system bus… Hard IP Cores – Can’t get internal access to… Full Scan Insertion – Increases overhead… It’s Too Late Anyway! – Re-spins are ENORMOUSLY expensive Co-Verification – Tools are cumbersome and slow – Modeling issues IO Pads Logic BIST Memory BIST Access Memory Array CPU Core IP Core Custom Boundary Scan TAP Controller Embedded System Bus Custom Logic Custom Core

4. For Academic Use Only Chipscope 4 Built For Debug - the Platform FPGA IO Pads Boundary Scan TAP Controller Embedded System Bus Memory Array PPC405 Core IP Core Custom Core ICON ILA IBA Custom Logic ILA FPGA Enables Full Internal Visibility – ChipScope Pro tools provide complete on-chip access Access Processor System Busses – ChipScope Pro Integrated Bus Analyzer Flexible On-Chip Debug – Small, efficient cores access any node or signal and can be removed at any time It’s Never Too Late in an FPGA! – Fix problems during development AND after product deployment Enable Complete System Verification – Debug systems in real-time – No need to extrapolate behavior

5. For Academic Use Only Chipscope 5 Traditional Logic Analysis Method Dedicated pins connected to logic analyzer External Logic Analyzer Pins Virtex-II Pro XC2VP20 FF1152 Probe points Requires Extensive Dedicated I/O for Debug – Driving signals to external I/O introduces additional problems Inflexible solution – Difficult or impossible to add additional debug pins if needed Limited visibility to on-chip activity

6. For Academic Use Only Chipscope 6 JTAG ChipScope Pro On-Chip Debug Integrated Logic Analyzer Core ChipScope Pro Virtex-II Pro XC2VP20 FF1152 ILABlock RAM Probe points No I/O pins required for debug – Access via the JTAG Port On-Chip access to every signal and node in the FPGA design – Driving signals to external I/O introduces additional problems Add and remove cores at any time in the design process

7. For Academic Use Only Chipscope 7 ChipScope Pro On-Chip Debug Integrated Bus Analyzer Core ChipScope Pro JTAG Virtex-II Pro XC2VP20 FF1152 IBABlock RAM System Busses No I/O pins required for debug – Access via the JTAG Port On-Chip System Bus Analysis – ChipScope Pro Integrated Bus Analysis of the CoreConnect On-Chip Peripheral bus (OPB) – Includes transaction debug and protocol violation detection

8. For Academic Use Only Chipscope 8 Aurora OPB SDRAM User Logic PLB Bus OPB Bus Bridge OPB GPIO Arbiter Choose the Core that Best Meets Your Design Requirements Integrated Bus Analysis Core (IBA) PLB and OPB specific Bus analysis cores Protocol detection Debug and verify control, address, and data buses Agilent Trace Core 2 (ATC2) Agilent created core enabling On-chip debug of Xilinx FPGAs using Agilent FPGA Dynamic Probing Virtual Input Output Core (VIO) Virtual Inputs and Outputs Stimulate logic with pulse trains Integrated Logic Analysis Core (ILA) Access internal nodes and signals Debug and verify signal behavior Define detailed trigger conditions

9. For Academic Use Only Chipscope 9 Debug Logic Anywhere Within the FPGA Clock Trigger 0 Trigger 1 Trigger 2 Trigger 3 Trigger Out Memory Controller Memory Controller Address Data Clock ILA Identify logic that you need to debug and verify ChipScope Pro cores are placed directly within the logic and … – Function as “virtual test headers” – Provide access any signal or node with the FPGA – Debug at the system clock rate

10. For Academic Use Only Chipscope 10 ChipScope Pro Tools Allow You to Add Cores at Any Time in the Design ChipScope Pro Core Generator – Generate and add cores at the beginning of the design process ChipScope Pro Core Inserter – Target existing signals and generate and insert cores into a synthesized design ChipScope Pro configuration – Simplify iterative debug and verification process

11. For Academic Use Only Chipscope 11 ChipScope Pro Interface Makes FPGA Debug Easy Access ChipScope cores via JTAG or user defined Trace port Configure FPGA, define trigger conditions, and view data via ChipScope Pro analyzer running on a PC ChipScope Pro Analyzer functions as a logic analyzer, bus analyzer, and control console

12. For Academic Use Only Chipscope 12 ChipScope Pro Analyzer server connected to Xilinx development board enabled for remote debug and verification Remote Debug and Verification Debug remote systems from your office via ChipScope Pro Analyzer client ChipScope Pro Analyzer server connected to fielded system enabled for remote debug and verification

13. For Academic Use Only Chipscope 13 Measures new groups of internal FPGA signals in seconds without –Recompiling the design –Impacting the timing of the design Save 15 min to 10 hours per new measurement Achieves wider internal visibility over a fixed number of pins –64 internal probe points for every pin conserves FPGA resources Save 8 hours per problem by not having to create a testbench Eliminates error prone & time consuming tasks –Automates signal/bus labeling from FPGA design to logic analyzer –Automatically maps FPGA pins from board layout to logic analysis channels Save 2 to 30 minutes per new measurement Exclusive Capability Combines On-Chip Debug with External Logic Analysis

14. For Academic Use Only Chipscope 14 Compatibility Xilinx FPGAs Virtex-4 Virtex-II Pro Virtex-II Spartan-3E Spartan-3 Core insertion/distribution ChipScope Pro ISE design software JTAG Cable Support Xilinx MultiLINK Parallel, Xilinx MultiLINX USB, Xilinx Parallel-IV Agilent Logic Analyzers 1680-series 1690-series 16900-series with following modules: 16740 series 16750 series 16910 series 16950 series Probing Soft touch, mictor, samtec, flying lead,

15. For Academic Use Only Chipscope 15 Xilinx ChipScope Pro Enabling Complete FPGA Debug Solutions IBA (EDK Integration) ILA, VIO FPGA Dynamic Probing System Complexity Debug and Verification Resources (Deep Storage, Complex Triggers) ILA, VIO

16. For Academic Use Only Chipscope 16 What’s Next View the ChipScope Pro product demo onlineonline – Learn how to insert ChipScope Pro cores into a design – Learn how to use the ChipScope Pro analyzer to debug and verify ChipScope Pro for the engineering curriculum – Donations available to Professors – www.xilinx.com/univ