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1 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) CPRE 583 Reconfigurable Computing Lecture 2:

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1 1 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) CPRE 583 Reconfigurable Computing Lecture 2: Fri 8/28/2009 (Reconfigurable Computing Hardware, VHDL Overview 2) Instructor: Dr. Phillip Jones (phjones@iastate.edu) Reconfigurable Computing Laboratory Iowa State University Ames, Iowa, USA http://class.ece.iastate.edu/cpre583/

2 2 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Logic Interconnect/Routing Optimized resources –Adders, Multipliers –Memory –System-on-chip building blocks Example Commercial FPGA structure VHDL review Overview

3 3 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Basic understanding of the major components that make up an FPGA device. VDHL is NOT a programming language. It is a means to describe hardware. What you should learn

4 4 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Basic FPGA Architectural Components FPGA: Field Programmable Gate Array Sea of general purpose logic gates CLB Configurable Logic Block (CLB)

5 5 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Computational Fabric - LUT 4-LUT Z LUT = Look up Table 0000 0001 1110 1111 ABCD Z B C D A 0000 0001 1110 1111 ABCD Z 00010001 AND Z A B C D 0000 0001 1110 1111 ABCD Z 01110111 OR Z A B C D X000 X001 X010 X101 X110 X111 ABCD Z 010011010011 B 2:1 Mux C D Z 1010

6 6 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Computational Fabric - LUT 4-LUT Z LUT = Look up Table B C D A How many 4-LUTs needed to OR 32-bits Draw 32 1

7 7 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Computational Fabric - LUT 4-LUT Z LUT = Look up Table B C D A How many 4-LUTs needed to OR 32-bits Draw 32 1 4 LUT 4 LUT 4 LUT 4 LUT

8 8 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Computational Fabric - LUT 4-LUT Z LUT = Look up Table B C D A How many 4-LUTs needed to AND 2-bits with the 32-bit OR Draw 32 1 4 LUT 4 LUT 4 LUT 4 LUT

9 9 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Computational Fabric - LUT 4-LUT Z LUT = Look up Table B C D A How many 4-LUTs needed to AND 2-bits with the 32-bit OR Draw 32 1 4 LUT 4 LUT 4 LUT 4 LUT

10 10 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Computational Fabric - LUT 4-LUT Z LUT = Look up Table B C D A How many 4-LUTs needed to AND 2-bits with the 32-bit OR Draw 32 1 4 LUT 4 LUT 4 LUT 4 LUT 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Write out the Truth table ABCD Z

11 11 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Computational Fabric - LUT 4-LUT Z LUT = Look up Table B C D A How many 4-LUTs needed to AND 2-bits with the 32-bit OR Draw 32 1 4 LUT 4 LUT 4 LUT 4 LUT 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 000000000000000000000000 Write out the Truth table ABCD Z

12 12 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Computational Fabric - LUT 4-LUT Z LUT = Look up Table B C D A How many 4-LUTs needed to AND 2-bits with the 32-bit OR Draw 32 1 4 LUT 4 LUT 4 LUT 4 LUT 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 00000001000000110000000100000011 Write out the Truth table ABCD Z

13 13 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Computational Fabric - LUT 4-LUT Z LUT = Look up Table B C D A How could one build a 4-LUT? 000001000001 1x16 Memory 16:1 Mux 4 ABCD Z

14 14 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Computational Fabric - LUT 4-LUT Z LUT = Look up Table B C D A How many different 4 input functions can a 4-LUT implement? 000001000001 1x16 Memory 16:1 Mux 4 ABCD Z 2 16 = 65536

15 15 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Computational Fabric - LUT 4-LUT Z LUT = Look up Table B C D A How many different N input functions can a N-LUT implement? 000001000001 1x16 Memory 16:1 Mux 4 ABCD Z

16 16 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Computational Fabric - LUT 4-LUT Z LUT = Look up Table B C D A How many different N input functions can a N-LUT implement? 000001000001 1x16 Memory 16:1 Mux N ABCD Z

17 17 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Computational Fabric - LUT 4-LUT Z LUT = Look up Table B C D A How many different N input functions can a N-LUT implement? 000001000001 1x2 N Memory 16:1 Mux N ABCD Z 2 16 =2 2 4 =65536 N = 4 = 2 2 N

18 18 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Granularity of Computational Trade-offs associated with LUT size Example: 2-LUT (4=2x2 bits) vs. 10-LUT (1024=32x32 bits) 1024-bits 2-LUT 10-LUT Microprocessor

19 19 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Granularity of Computational Trade-offs associated with LUT size Example: 2-LUT (4=2x2 bits) vs. 10-LUT (1024=32x32 bits) 1024-bits 2-LUT 10-LUT Microprocessor 4 3 3 A B op 3

20 20 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Granularity of Computational Trade-offs associated with LUT size Example: 2-LUT (4=2x2 bits) vs. 10-LUT (1024=32x32 bits) 1024-bits 2-LUT 10-LUT Microprocessor 4 3 3 A B op 3 4 3 3 A B 3 4 3 3 A B 3

21 21 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Granularity of Computational Trade-offs associated with LUT size Example: 2-LUT (4=2x2 bits) vs. 10-LUT (1024=32x32 bits) 1024-bits 2-LUT 10-LUT Microprocessor 4 3 3 A B op 3 4 3 3 A B 3 3 3 3 A B

22 22 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Granularity of Computational Trade-offs associated with LUT size Example: 2-LUT (4=2x2 bits) vs. 10-LUT (1024=32x32 bits) 1024-bits 2-LUT 10-LUT Microprocessor 4 3 3 A B op 3

23 23 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Granularity of Computational Trade-offs associated with LUT size Example: 2-LUT (4=2x2 bits) vs. 10-LUT (1024=32x32 bits) 1024-bits 2-LUT 10-LUT Bit logic and constants

24 24 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Granularity of Computational Trade-offs associated with LUT size Example: 2-LUT (4=2x2 bits) vs. 10-LUT (1024=32x32 bits) 1024-bits 2-LUT 10-LUT Bit logic and constants (A and “1100”) or (B or “1000”)

25 25 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Granularity of Computational Trade-offs associated with LUT size Example: 2-LUT (4=2x2 bits) vs. 10-LUT (1024=32x32 bits) 1024-bits 2-LUT 10-LUT Bit logic and constants (A and “1100”) or (B or “1000”) A B

26 26 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Granularity of Computational Trade-offs associated with LUT size Example: 2-LUT (4=2x2 bits) vs. 10-LUT (1024=32x32 bits) 1024-bits 2-LUT 10-LUT Bit logic and constants (A and “1100”) or (B or “1000”) A AND OR 1 0 B 4 4 It’s much worse, each 10-LUT only has one output Area that was required using 2-LUTS

27 27 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) LUTs are fine for implementing any arbitrary combinational logic (output is ONLY a function of its inputs) function. But what about sequential logic (output is a function of input AND previous state information)? Computational Fabric - DFF 4-LUT Z B C D A Need Memory!!

28 28 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Computational Fabric - DFF 4-LUT Z(t) B C D A DFF Z(t+1) 1/0 0/0 1111101101 1/0 0/0 1/1 0/0 Start 1/0 Input/output Detect the pattern “1101” DFF = D Flip Flop

29 29 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Computational Fabric - DFF 4-LUT Z(t) B C D A DFF Z(t+1) Increase circuit performance (pipelining) 4-LUT B C D A DFF 4-LUT DFF 4-LUT DFF 4-LUT DFF 4 LUT delays per output 4-LUT B C D A DFF 4-LUT DFF 4-LUT DFF 4-LUT DFF 1 DFF delay per output DFF = D Flip Flop

30 30 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Need a mechanism to move results of computation around. Communication: Interconnect & Routing CLB

31 31 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Need a mechanism to move results of computation around. Communication: Interconnect & Routing Nearest Neighbor: CLB

32 32 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Need a mechanism to move results of computation around. Communication: Interconnect & Routing CLB Nearest Neighbor: Segmented: CLB

33 33 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Need a mechanism to move results of computation around. Communication: Interconnect & Routing Nearest Neighbor: Segmented: Hierarchical: CLB

34 34 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) LUTs + DFFs can implement any arbitrary digital logic. But not optimally (ASICs give make much better use of silicon area for Power, Speed, routing resources) Arithmetic –Add, Multiply On chip memory System on chip building blocks –Processor, PCI-express, Gigabit Ethernet, ADC, etc. Optimized Resources: Dedicated Logic

35 35 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Optimized Resources: Dedicated Logic Carry Look Ahead c4 Carry in Carry out 6-LUT A3A3 B3B3 A2A2 B2B2 A1A1 B1B1 Sum 3 Sum 2 Sum 1 G1 P1 Sum 1 CLB P2 Carry 2 G2 CLB Sum 2 A1A1 B1B1 A1A1 B1B1 A1A1 B1B1 Carry 1 A2A2 B2B2 Fast Addition Two output LUT generate propagate logic Dedicated routing resources

36 36 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Optimized Resources: Dedicated Logic Embedded Memory 8 12 96 bits, 300 MHz

37 37 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Optimized Resources: Dedicated Logic Dedicated memory block Embedded Memory 8 12 18 Kbits, 550 MHz

38 38 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Optimized Resources: Dedicated Logic Multiplication Type# LUTsLatencySpeed LUT ~4005 clks380 MHz Dedicated 18x18 Multiplier 03 clks450 MHz Virtex-5 (6-LUTs) 18x18 multiply Very rough estimate of Silicon area comparison (assuming SX95 andLX110 have about the same die size) 6-LUT 18x18 Multiplier In other word you can replace one LUT based 18x18 multiplier With 100 dedicated 18x18 Multipliers!!!

39 39 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Optimized Resources: Dedicated Logic Processor PowerPC hard-core MicroBlaze soft-core 500 MHz Super scalor Highspeed 2x5 switch fabric 250 MHz Simple scalar

40 40 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Optimized Resources: Dedicated Logic System on Chip Ethernet MAC RAM Motor PID Controller Sensor ADC Sensor Data Buffer Dedicated Logic Reconfigurable Logic Matrix Multiplier Coprocessor Also see Actel Fusion:http://www.actel.com/products/fusion/default.aspxhttp://www.actel.com/products/fusion/default.aspx

41 41 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Xilinx CLB Architecture (in 30 seconds) Virtex 5 FPGA User Guide

42 42 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) VHDL basics VHDL: (V)HSIC (H)ardware (D)escription (L)anguage –VHSIC: (V)ery (H)igh (S)peed (I)ntegrated (C)ircuit It is NOT a programming language!!! It is a Hardware Description Language (HDL) Conceptually VERY different form C,C++

43 43 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Some Key Differences from C C is inherently sequential (serial), one statement executed at a time VHDL is inherently concurrent (parallel), many statements execute (simulate) at a time

44 44 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Some Key Differences from C C example VHDL example A = B + C X = Y + Z Ans = A + X Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X Current Values: A = 1 B = 1 C = 1 X = 1 Y = 1 Z = 1 Ans = 1 Current Values: A = 1 B = 1 C = 1 X = 1 Y = 1 Z = 1 Ans = 1

45 45 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Some Key Differences from C C example VHDL example A = B + C X = Y + Z Ans = A + X Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X Current Values: A = 2 B = 1 C = 1 X = 1 Y = 1 Z = 1 Ans = 1 Current Values: A = 1 B = 1 C = 1 X = 1 Y = 1 Z = 1 Ans = 1

46 46 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Some Key Differences from C C example VHDL example A = B + C X = Y + Z Ans = A + X Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 1 Current Values: A = 1 B = 1 C = 1 X = 1 Y = 1 Z = 1 Ans = 1

47 47 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Some Key Differences from C C example VHDL example A = B + C X = Y + Z Ans = A + X Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 4 Current Values: A = 1 B = 1 C = 1 X = 1 Y = 1 Z = 1 Ans = 1

48 48 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Some Key Differences from C C example VHDL example A = B + C X = Y + Z Ans = A + X Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 4 Current Values: A = 1 B = 1 C = 1 X = 1 Y = 1 Z = 1 Ans = 1 “Simulates in parallel ever delta time step” Show impact Of changing Order of statements

49 49 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Some Key Differences from C C example VHDL example A = B + C X = Y + Z Ans = A + X Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 4 Current Values: A = 1 B = 1 C = 1 X = 1 Y = 1 Z = 1 Ans = 1 “Simulates in parallel ever delta time step” Snap shot after input change

50 50 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Some Key Differences from C C example VHDL example A = B + C X = Y + Z Ans = A + X Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 4 Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 2 “Simulates in parallel ever delta time step”

51 51 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Some Key Differences from C C example VHDL example A = B + C X = Y + Z Ans = A + X Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 4 Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 2 “Simulates in parallel ever delta time step” Different

52 52 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Some Key Differences from C C example VHDL example A = B + C X = Y + Z Ans = A + X Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 4 Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 2 “Simulates in parallel ever delta time step” Snap shot after input change

53 53 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Some Key Differences from C C example VHDL example A = B + C X = Y + Z Ans = A + X Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 4 Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 2 “Simulates in parallel ever delta time step”

54 54 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Some Key Differences from C C example VHDL example A = B + C X = Y + Z Ans = A + X Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 4 Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 4 “Simulates in parallel ever delta time step”

55 55 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Corresponding circuit VHDL example Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X “Simulates in parallel ever delta time step”

56 56 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Corresponding circuit VHDL example Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X “Simulates in parallel ever delta time step” + + B(1) C(1) Y(1) Z(1) + A(1) X(1) Ans(1)

57 57 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Corresponding circuit VHDL example Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X “Simulates in parallel ever delta time step” + + B(1) C(1) Y(1) Z(1) + A(2) X(2) Ans(2)

58 58 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Corresponding circuit VHDL example Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X “Simulates in parallel ever delta time step” + + B(1) C(1) Y(1) Z(1) + A(2) X(2) Ans(4)

59 59 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Corresponding circuit (More realistic) VHDL example Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C after 2ns X <= Y + Z after 2ns Ans <= A + X after 2ns “Simulates in parallel ever delta time step” + + B(1) C(1) Y(1) Z(1) + A(1) X(1) Ans(1) 2ns

60 60 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) VHDL example Initially: A,B,C,X,Y,Z,Ans =1 “Simulates in parallel ever delta time step” + + B(1) C(1) Y(1) Z(1) + A(2) X(2) Ans(2) Corresponding circuit (More realistic) 2ns A <= B + C after 2ns X <= Y + Z after 2ns Ans <= A + X after 2ns

61 61 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) VHDL example Initially: A,B,C,X,Y,Z,Ans =1 “Simulates in parallel ever delta time step” + + B(1) C(1) Y(1) Z(1) + A(2) X(2) Ans(4) Corresponding circuit (More realistic) 2ns A <= B + C after 2ns X <= Y + Z after 2ns Ans <= A + X after 2ns

62 62 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Typical Structure of a VHDL File LIBRARY ieee; ENTITY test_circuit IS PORT(B,C,Y,Z,Ans); END test_circuit; ARCHITECTURE structure OF test_circuit IS signal A : std_logic_vector(7 downto 0); signal X : std_logic_vector(7 downto 0); BEGIN A <= B + C; X <= Y + Z; Ans <= A + X; END Include Libraries Define component name and Input/output ports Declare internal signals, components Implement components functionality

63 63 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Process Process provide a level serialization in VHDL (e.g. variables, clocked processes) Help separate and add structure to VHDL design

64 64 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Process Example BEGIN My_process_1 : process (A,B,C,X,Y,Z) Begin A <= B + C; X <= Y + Z; Ans <= A + X; End My_process_1; My_process_2 : process (B,X,Y,Ans1) Begin A <= B + 1; X <= B + Y; Ans2 <= Ans1 + X; End My_process_2; END; Sensitivity list: specify inputs to the process. Process is updated when a specified input changes

65 65 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Process Example (Multiple Drivers) BEGIN My_process_1 : process (A,B,C,X,Y,Z) Begin A <= B + C; X <= Y + Z; Ans <= A + X; End My_process_1; My_process_2 : process (B,X,Y,Ans1) Begin A <= B + 1; X <= B + Y; Ans2 <= Ans1 + X; End My_process_2; END; A signal can only be Driven (written) by one process. But can be read by many Compile or simulator may give a “multiple driver” Error or Warning message

66 66 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Process Example (Multiple Drivers) BEGIN My_process_1 : process (A,B,C,X,Y,Z) Begin A <= B + C; X <= Y + Z; Ans <= A + X; End My_process_1; My_process_2 : process (B,X,Y,Ans1) Begin A1 <= B + 1; X1 <= B + Y; Ans2 <= Ans1 + X; End My_process_2; END; Maybe A,X were suppose to be A1,X1. Cut and paste error. Or may need to rethink Hardware structure to remove multiple driver issue.

67 67 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Process Example (if-statement) BEGIN My_process_1 : process (A,B,C,X,Y,Z) Begin if (B = 0) then C <= A + B; Z <= X + Y; Ans1 <= A + X; else C <= 1; Z <= 0; Ans1 <= 1; end if; End My_process_1; END; Add circuit

68 68 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Clock Process Example BEGIN My_process_1 : process (clk) Begin IF (clk’event and clk = ‘1’) THEN C <= A or B; Z <= X or Y; Ans <= C and Z; END IF; End My_process_1; END; or A() B() X() Y() and C() Z() Ans() circuit not clocked

69 69 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Clock Process Example BEGIN My_process_1 : process (clk) Begin IF (clk’event and clk = ‘1’) THEN C <= A or B; Z <= X or Y; Ans <= C and Z; END IF; End My_process_1; END; or A() B() X() Y() and C() Z() Ans() circuit with clock clk D Flip-Flop DFF Register

70 70 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Clock Process Example BEGIN My_process_1 : process (clk) Begin IF (clk’event and clk = ‘1’) THEN C <= A or B; Z <= X or Y; Ans <= C and Z; END IF; End My_process_1; END; or A() B() X() Y() and C() Z() Ans() circuit with clock clk

71 71 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Clock Process Example 2 BEGIN My_process_1 : process (clk) Begin IF (clk’event and clk = ‘1’) THEN C <= A xor B; Z <= X or Y; Ans <= C xor Z; END IF; End My_process_1; END; xor or A() B() X() Y() xor C() Z() Ans() circuit with clock clk

72 72 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Clock Process Example 2 (Answer) BEGIN My_process_1 : process (clk) Begin IF (clk’event and clk = ‘1’) THEN C <= A xor B; Z <= X or Y; Ans <= C xor Z; END IF; End My_process_1; END; xor or A() B() X() Y() xor C() Z() Ans() circuit with clock clk

73 73 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) VHDL Constructs Entity Process Signal, Variable, Constants, Integers Array, Record VHDL on-line tutorials: http://www.seas.upenn.edu/~ese201/vhdl/vhdl_primer.html http://www.vhdl-online.de/tutorial/

74 74 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Signals and Variables Signals –Updated at the end of a process –Have file scope Variables –Updated instantaneously –Have process scope VHDL on-line tutorials: http://www.seas.upenn.edu/~ese201/vhdl/vhdl_primer.html http://www.vhdl-online.de/tutorial/

75 75 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) std_logic, std_logic_vector Very common data types std_logic –Single bit value –Values: U, X, 0, 1, Z, W, H, L, - –Example: signal A : std_logic; A <= ‘1’; Std_logic_vector: is an array of std_logic –Example: signal A : std_logic_vector (4 downto 0); A <= x“00Z001” VHDL on-line tutorials: http://www.seas.upenn.edu/~ese201/vhdl/vhdl_primer.html http://www.vhdl-online.de/tutorial/

76 76 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Std_logic values –U : Uninitialized (signal has not been assigned a value yet) –X : Unknow (2 drivers one ‘0’ one ‘1’) –H : weak ‘1’ (example: model pull-up resister) I have never used this value –L : weak ‘0’ Time step 0

77 77 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Std_logic values –U : Uninitialized (signal has not been assigned a value yet) –X : Unknow (2 drivers one ‘0’ one ‘1’) –H : weak ‘1’ (example: model pull-up resister) I have never used this value –L : weak ‘0’ Time step 0 1 UUU Std_logic values

78 78 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Std_logic values –U : Uninitialized (signal has not been assigned a value yet) –X : Unknow (2 drivers one ‘0’ one ‘1’) –H : weak ‘1’ (example: model pull-up resister) I have never used this value –L : weak ‘0’ Time step 1 0 1UU Std_logic values

79 79 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Std_logic values –U : Uninitialized (signal has not been assigned a value yet) –X : Unknow (2 drivers one ‘0’ one ‘1’) –H : weak ‘1’ (example: model pull-up resister) I have never used this value –L : weak ‘0’ Time step 2 1 01U Std_logic values

80 80 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Std_logic values –U : Uninitialized (signal has not been assigned a value yet) –X : Unknow (2 drivers one ‘0’ one ‘1’) –H : weak ‘1’ (example: model pull-up resister) I have never used this value –L : weak ‘0’ Time step 3 1 101 Std_logic values

81 81 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Std_logic values –U : Uninitialized (signal has not been assigned a value yet) –X : Unknow (2 drivers one ‘0’ one ‘1’) –H : weak ‘1’ (example: model pull-up resister) I have never used this value –L : weak ‘0’ Time step 3 1 101 0 1 X Std_logic values

82 82 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Std_logic values –U : Uninitialized (signal has not been assigned a value yet) –X : Unknow (2 drivers one ‘0’ one ‘1’) –H : weak ‘1’ (example: model pull-up resister) I have never used this value –L : weak ‘0’ Time step 3 1 101 0 1 X 1 0 Std_logic values

83 83 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Std_logic values –U : Uninitialized (signal has not been assigned a value yet) –X : Unknow (2 drivers one ‘0’ one ‘1’) –H : weak ‘1’ (example: model pull-up resister) I have never used this value –L : weak ‘0’ Time step 3 1 11X 0 0 X 1 X Std_logic values

84 84 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Std_logic values –U : Uninitialized (signal has not been assigned a value yet) –X : Unknow (2 drivers one ‘0’ one ‘1’) –H : weak ‘1’ (example: model pull-up resister) I have never used this value –L : weak ‘0’ Time step 0 ‘1’ Pull-up resistor Std_logic values

85 85 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Std_logic values –U : Uninitialized (signal has not been assigned a value yet) –X : Unknow (2 drivers one ‘0’ one ‘1’) –H : weak ‘1’ (example: model pull-up resister) I have never used this value –L : weak ‘0’ Time step 0 0 U HU ‘1’ Pull-up resistor Std_logic values

86 86 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Std_logic values –U : Uninitialized (signal has not been assigned a value yet) –X : Unknow (2 drivers one ‘0’ one ‘1’) –H : weak ‘1’ (example: model pull-up resister) I have never used this value –L : weak ‘0’ Time step 1 1 0 H1 ‘1’ Pull-up resistor Std_logic values

87 87 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Std_logic values –U : Uninitialized (signal has not been assigned a value yet) –X : Unknow (2 drivers one ‘0’ one ‘1’) –H : weak ‘1’ (example: model pull-up resister) I have never used this value –L : weak ‘0’ Time step 2 0 1 01 ‘1’ Pull-up resistor Resolution(H,0) = 0 Std_logic values

88 88 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) mysignal’event (mysignal changed value) mysignal’high (highest value of mysignal’s type) mysignal’low Many other attributes –http://www.cs.umbc.edu/help/VHDL/summary.htmlhttp://www.cs.umbc.edu/help/VHDL/summary.html Pre-defined VHDL attributes

89 89 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Signal: global to file Variable: local to process Singal vs Varible scope VHDL on-line tutorials: http://www.seas.upenn.edu/~ese201/vhdl/vhdl_primer.html http://www.cs.umbc.edu/help/VHDL/summary.html http://www.vhdl-online.de/tutorial/ My_process_1 : process (B,C,Y) Begin A <= B + C; Z <= Y + C; End My_process_1; My_process_2 : process (B,X,Y,Ans1) Begin X <= Z + 1; Ans <= B + Y; End My_process_2;

90 90 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Signal: global to file Variable: local to process Singal vs Varible scope VHDL on-line tutorials: http://www.seas.upenn.edu/~ese201/vhdl/vhdl_primer.html http://www.cs.umbc.edu/help/VHDL/summary.html http://www.vhdl-online.de/tutorial/ My_process_1 : process (B,C,Y) Begin A <= B + C; varZ <= Y + C; End My_process_1; My_process_2 : process (B,X,Y,Ans1) Begin X <= varZ + 1; Ans <= B + Y; End My_process_2; Each varZ are local to their process. Completely independent

91 91 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Arrays and Records Arrays: Group signals of the same type together Records: Group signal of different types together VHDL on-line tutorials: http://www.seas.upenn.edu/~ese201/vhdl/vhdl_primer.html http://www.vhdl-online.de/tutorial/

92 92 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Array Example (Delay Shift Register) VHDL on-line tutorials: http://www.seas.upenn.edu/~ese201/vhdl/vhdl_primer.html http://www.vhdl-online.de/tutorial/ flag_inflag_1flag_2flag_3 flag_out BEGIN My_process_1 : process (clk) Begin IF (clk’event and clk = ‘1’) THEN flag_1 <= flag_in; flag_2 <= flag_1; flag_3 <= flag_2; END IF; End My_process_1; flag_out <= flag_3 END;

93 93 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Array Example (Delay Shift Register) flag_inflag_1flag_20 flag_out BEGIN My_process_1 : process (clk) Begin IF (clk’event and clk = ‘1’) THEN flag_reg(flag_reg'high downto 0) <= flag_reg(flag_reg'high-1 downto 0) & flag_in; END IF; End My_process_1; flag_out <= flag_reg(flag_reg'high); END; type flag_reg_array is array (DELAY-1 downto 0) of std_logic; signal flag_reg : flag_reg_array;

94 94 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Array Example (Delay Shift Register) VHDL on-line tutorials: http://www.seas.upenn.edu/~ese201/vhdl/vhdl_primer.html http://www.vhdl-online.de/tutorial/ flag_inflag_1flag_20 flag_out BEGIN My_process_1 : process (clk) Begin IF (clk’event and clk = ‘1’) THEN flag_1 <= flag_in; flag_2 <= flag_1; flag_20 <= flag_19; END IF; End My_process_1; flag_out <= flag_20 END;

95 95 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Array Example (Delay Shift Register) flag_reg(flag_reg'high downto 0)<= flag_reg(flag_reg'high-1 downto 0) & flag_in; flag_inflag(0)flag(1)flag(2) flag_out 001 1 flag_inflag(0)flag(1)flag(2) flag_out 001 1 flag_inflag(0)flag(1)flag(2) flag_out 100

96 96 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Array Example (Delay Shift Register) VHDL on-line tutorials: http://www.seas.upenn.edu/~ese201/vhdl/vhdl_primer.html http://www.vhdl-online.de/tutorial/ flag_inflag_0flag_1flag_2 flag_out BEGIN My_process_1 : process (clk) Begin IF (clk’event and clk = ‘1’) THEN flag_1 <= flag_in; flag_2 <= flag_1; flag_3 <= flag_2; END IF; End My_process_1; flag_out <= flag_3 END;

97 97 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) N-Lut, 3,4…6,…8-LUT –AND, XOR, NOT –Exercises How many 4-LUTs to OR 32 bits (draw) How many 4-LUTs to AND 2 bits with the OR of these 32 bits (draw) Draw the truth table for the 4-LUT that gives the final output –How could one implement a LUT (Memory + MUX) –How many ways can a 4-LUT be programmed –How many ways can a N-LUT be programmed Granularity trade-off: Functionality vs. propagation delay (2-LUT -> CPU), bit-level vs. datapath Computational Fabric - LUT

98 98 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Enable building circuits that can store information (sequential circuits, state machines) Enables pipelining to increase operating frequency/ throughput Computational Fabric - DFF

99 99 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Need a mechanism to move the results of a LUT to other LUTs. Island stale (Array of CB) –Nearest neighbor (paper on reconfigure arch that uses this) Not scalable (large delays, and uses logic elements for routing?) –Segmented (different length for latency trade-off) Multi hop scales < O(N)? Avoid using logic –Hierarchical (good for apps with lots of local communication and little remote communication) Typical an FPGA silicon area will be 10% logic and 90% interconnect!! Communication: Interconnect & Routing

100 100 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) LUTs + DFFs can implement any arbitrary digital logic. But not optimally (ASICs give make much better use of silicon area for Power, Speed, routing resources) Arithmetic –Add, Mult On chip memory System on chip building blocks –Processor, PCI-express, Gigbit Ethernet, A/D Optimized Resources: Hard Cores

101 101 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Blank Xilinx CLB?

102 102 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing HW, VHDL 2 Iowa State University (Ames) Build on top of last year, refine, reevaluate VHDL basics

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