1. Dec 3, 2008Sheth: MS Thesis1 A Hardware-Software Processor Architecture Using Pipeline Stalls For Leakage Power Management Khushboo Sheth Master’s Thesis Defense December 3, 2008 Thesis Committee: Dr. Vishwani Agrawal, Advisor Dr. Victor Nelson Dr. Adit Singh Dec 3, 2008 1 Sheth: MS Thesis

2. Dec 3, 2008Sheth: MS Thesis2 Outline   Motivation   Background   NOP-cycle method for energy saving   Comparison of Reference method with NOP- cycle method   Architecture Modification   Power Management Techniques   Sleep mode operation   Drowsy mode operation   Conclusion

3. Dec 3, 2008Sheth: MS Thesis3 Power components in CMOS circuit V DD Ground CLCL R on R=large v i (t) v o (t) Dynamic power Short circuit power Leakage power

4. Dec 3, 2008Sheth: MS Thesis4 Motivation   Technology scaling Per transistor dynamic power decreases Per transistor leakage power increases Number of transistors increase   Contribution of Leakage increases Reduction in threshold voltage Leakage Gate size Power Density

5. Dec 3, 2008Sheth: MS Thesis5 Processor Power Trend   Processor power increases every generation

6. Dec 3, 2008Sheth: MS Thesis6 Objective of This Work  Explore power management for a processor at the architecture level.  Reduce power and minimize leakage energy.  Propose and evaluate a new hardware- software technique for power management. Dec 3, 2008 6 Sheth: MS Thesis

7. Dec 3, 2008Sheth: MS Thesis7 Background  A simple technique to reduce power is to slow-down the clock: Dynamic power reduced in proportion to clock rate. Dynamic power reduced in proportion to clock rate. Leakage power remains unchanged. Leakage power remains unchanged. A computing task takes longer in the power saving mode: A computing task takes longer in the power saving mode: Consumes the same dynamic energyConsumes the same dynamic energy Consumes more leakage energyConsumes more leakage energy  We use this as a reference method. Dec 3, 2008 Sheth: MS Thesis 7

8. Dec 3, 2008Sheth: MS Thesis8 Clock-Slowdown (Reference) Method  Normal operation: Rated clock frequency, fRated clock frequency, f Dynamic power, PdDynamic power, Pd Static power, PsStatic power, Ps Total power, Pd + PsTotal power, Pd + Ps Energy consumed by an N-cycle task = (Pd + Ps) N/fEnergy consumed by an N-cycle task = (Pd + Ps) N/f  Power saving mode: Clock frequency, f/nClock frequency, f/n Dynamic Power, Pd/nDynamic Power, Pd/n Static Power, PsStatic Power, Ps Total power, P(n) = Pd/n +PsTotal power, P(n) = Pd/n +Ps Energy consumed by an N-cycle task, E(N,n) = (Pd+ nPs) N/fEnergy consumed by an N-cycle task, E(N,n) = (Pd+ nPs) N/f Dec 3, 2008 Sheth: MS Thesis 8

9. Dec 3, 2008Sheth: MS Thesis9 Power Saving Ratio  P-ratio = P(1)/P(n) = n(Pd + Ps)/(Pd + nPs) = n(k+1)/(k+n), where k = Pd/Ps  Low leakage technology, k >> 1 P-ratio= n  High leakage technology, k ≤ 2 P-ratio= 3n/(n+2)for k = 2 = 2n/(n+1)for k = 1 = 3n/(2n+1)for k = 0.5 Dec 3, 2008 Sheth: MS Thesis 9

10. Dec 3, 2008Sheth: MS Thesis10 Power Saving Ratio, P-ratio Dec 3, 2008 Sheth: MS Thesis 10 Low leakage k >> 1 k = 2 k = 1 k = 0.5 P-ratio 5432154321 1 2 3 4 5 Clock slowdown factor, n

11. Dec 3, 2008Sheth: MS Thesis11 Energy Saving Ratio  E-ratio = E(N,1)/E(N,n) = (Pd + Ps)/(Pd + nPs)= n P-ratio = (k+1)/(k+n), where k = Pd/Ps  Low leakage technology, k >> 1 E-ratio= 1  High leakage technology, k ≤ 2 E-ratio= 3/(n+2)for k = 2 = 2/(n+1)for k = 1 = 3/(2n+1)for k = 0.5 Dec 3, 2008 Sheth: MS Thesis 11

12. Dec 3, 2008Sheth: MS Thesis12 Energy Saving Ratio, E-ratio Dec 3, 2008 Sheth: MS Thesis 12 Low leakage k >> 1 k = 2 k = 1 k = 0.5 1/E-ratio 4321043210 1 2 3 4 5 Clock slowdown factor, n No energy increase Energy increase →

13. Dec 3, 2008Sheth: MS Thesis13 Instruction Slowdown: New Energy Saving Method  Maintain rated clock frequency (f).  Instruction slowdown factor, m, where m ≥ 0; power management hardware inserts m nop’s per instruction.  Provide hardware sleep modes to reduce nop power: Power control signals generated by control logic Power control signals generated by control logic ALU powered downALU powered down Register file clocks gatedRegister file clocks gated Memory sleep modeMemory sleep mode Pipeline register clocks gatedPipeline register clocks gated Dec 3, 2008 Sheth: MS Thesis 13

14. Dec 3, 2008Sheth: MS Thesis14 Power Consumed With NOPs Dec 3, 2008 Sheth: MS Thesis 14 1 second (f cycles) f/(m+1) Instruction cycles Energy = P/(m+1) mf/(m+1) NOP cycles Energy = m βP/(m+1) P=Power consumed by instructions cycles P/f =energy consumed per instruction cycle βP/f =energy consumed per NOP cycle β=reduction factor (0≤β≤1) due to power down/sleep modes Power = P(1 + m β)/(m + 1)

15. Dec 3, 2008Sheth: MS Thesis15 NOP-Cycles Method NOP-Cycles Method  Normal operation: Rated clock frequency, f, m = 0Rated clock frequency, f, m = 0 Dynamic power, PdDynamic power, Pd Static power, PsStatic power, Ps Total power, Pd + PsTotal power, Pd + Ps Energy consumed by an N-cycle task = (Pd + Ps) N/fEnergy consumed by an N-cycle task = (Pd + Ps) N/f  Power saving mode: Clock frequency, fClock frequency, f Dynamic Power, Pd (1 + m β)/(m + 1)Dynamic Power, Pd (1 + m β)/(m + 1) Static Power, Ps (1 + m β)/(m + 1)Static Power, Ps (1 + m β)/(m + 1) Total power, P(m) = (Pd + Ps) (1 + m β)/(m + 1)Total power, P(m) = (Pd + Ps) (1 + m β)/(m + 1) Energy consumed by an N-cycle task,Energy consumed by an N-cycle task, E(N,m) = (Pd+Ps) [(1+m β)/(m+1)] N(m+1)/f = (Pd+Ps)(1+m β)N/f Dec 3, 2008 Sheth: MS Thesis 15

16. Dec 3, 2008Sheth: MS Thesis16 Power and Energy Saving Ratio  P-ratio =P(0) / P(m) =(m + 1) / (1 + m β)  E-ratio=E(N,0) / E(N,m) =1 / (1 + m β) Dec 3, 2008 Sheth: MS Thesis 16

17. Dec 3, 2008Sheth: MS Thesis17 Power Saving Ratio, P-ratio Dec 3, 2008 Sheth: MS Thesis 17 Ideal case β = 0 β = 0.1 β = 1 β = 0.5 P-ratio 5432154321 0 1 2 3 4 Instruction slowdown factor, m β = 0.33 Decreasing power →

18. Dec 3, 2008Sheth: MS Thesis18 Energy Saving Ratio, P-ratio Dec 3, 2008 Sheth: MS Thesis 18 β = 1 β = 0.5 β = 0 β = 0.1 1/E-ratio 5432154321 0 1 2 3 4 Instruction slowdown factor, m β = 0.33 Increasing energy →

19. Dec 3, 2008Sheth: MS Thesis19 Comparing Two Cases  Energy(Clock slowdown)/Energy(Instruction slowdown) k + m + 1 k + m + 1 =_____________ (k+1) (1+m β) (k+1) (1+m β) where, n = m+1, and k = Pd/Ps Dec 3, 2008 Sheth: MS Thesis 19

20. Dec 3, 2008Sheth: MS Thesis20 Clock Slowdown Vs. Instruction Slowdown, β = 1 (No Sleep Mode) Dec 3, 2008 Sheth: MS Thesis 20 k = 0.5 k = 1 k >> 1 Energy ratio 4321043210 0 1 2 3 4 Slowdown factor, m or n-1 k = 2 Advantage →

21. Dec 3, 2008Sheth: MS Thesis21 Clock Slowdown Vs. Instruction Slowdown, β = 0.5 (Sleep Mode) Dec 3, 2008 Sheth: MS Thesis 21 k = 0.5 k = 1 k >> 1 Energy ratio 4321043210 0 1 2 3 4 Slowdown factor, m or n-1 k = 2 Advantage →

22. Dec 3, 2008Sheth: MS Thesis22 Clock Slowdown Vs. Instruction Slowdown, β = 0.1 (Sleep Mode) Dec 3, 2008 Sheth: MS Thesis 22 k = 0.5 k = 1 k >> 1 Energy ratio 4321043210 0 1 2 3 4 Slowdown factor, m or n-1 k = 2 Advantage →

23. Dec 3, 2008Sheth: MS Thesis23 32 Bit MIPS pipeline processor

24. Dec 3, 2008Sheth: MS Thesis24 Modified Architecture Slow down signal ALU, Data memory and Register File put to sleep mode

25. Dec 3, 2008Sheth: MS Thesis25 Power Management Techniques   Clock Gating: Clock Signal halted in idle devices Switching activity reduced Leakage power unaffected A glitch can cause a temporarily false clock turn off/on   Enabled Flip Flops: Registers replaced by a representative with an enabled signal When disabled, outputs are not changing Reduces switching activity, but clock still active which consumes lot of power Less effective

26. Dec 3, 2008Sheth: MS Thesis26 Sleep Mode Operation   Activity of the entire system is monitored rather than that of the individual modules.   If the system has been idle for some predetermined time-out duration, then the entire system is shut down and enters what is known as sleep mode.   System inputs are monitored for activity, which will then trigger the system to wake up and resume processing.   Overhead in time and power associated with entering and leaving sleep mode.   Trade-offs to be made in setting the length of the desired time-out period.

27. Dec 3, 2008Sheth: MS Thesis27 Implementing Sleep Mode   Power-gating technique Suitably sized header or footer transistor for a circuit block Sleep signal applied to the gate of the header or footer transistor to turn-off the supply voltage of the circuit block When circuit block is being requested for use, the sleep signal is de-asserted to restore the voltage at the virtual Vdd.

28. Dec 3, 2008Sheth: MS Thesis28 Drowsy mode for memories   To retain any information stored in the memory cells when switched to low- power mode drowsy mode provides a better solution   High-threshold (high-Vt) transistor used to separate virtual Vdd from Vdd supply line   Supplies a very low voltage to the cell when it is turned in to low power mode   High-Vt device drastically reduces the leakage of the circuit because of the exponential dependence of leakage on Vt

29. Dec 3, 2008Sheth: MS Thesis29 Conclusion   For the higher-leakage technologies, hardware-software technique inserts pipeline stalls in the processor while maintaining the clock rate of the processor. The hardware units are designed to save leakage power while processing NOP instruction by putting the idle blocks into sleep mode.   This technique is more effective when NOP cycle consumes less than 50% power than regular instruction cycle   Future work includes considering the power of the active cycles and applying voltage reduction when reducing the clock frequency, if the performance penalty can be met.

30. Dec 3, 2008Sheth: MS Thesis30 References   P. Lotfi-Kamran, A. Rahmani, A. Salehpour, A. Afzali-Kusha, and Z. Navabi, “Stall Power Reduction in Pipelined Architecture Processors”, in Proc. of 21 st International Conference on VLSI Design, 2008, pp.541-546.   K. Najeeb, V. V. R. Konda, S. S. Hari, V. Kamakoti, and V. M. Vedula, “Power Virus Generation Using Behavioral Models of Circuits”, in Proc. 25 th IEEE VLSI Test Symposium, 2007, pp.35-40.   B. Yu and M. L. Bushnell, “A Novel Dynamic Power Cut-off Technique (DPCT) for Active Leakage Reduction in Deep Submicron CMOS Circuits”, in Proc. International Symposium On Low Power Electronics and Design, 2006, pp. 214-219.   K. Flautner, N. S. Kim, S. Martin, D. Blaauw, and T. Mudge, “Drowsy Caches: Simple Techniques for Reducing Leakage Power”, in Proc. International Symposium on Computer Architecture, 2002, pp.148-157.   Z. Hu, A. Buyuktosunoglu, V. Srinivasan, V. Zyuban, H. Jacobson, and P. Bose, “Microarchitectural Techniques for Power Gating of Execution Units”, in International Symposium on Low Power Electronics and Design, 2004, pp. 32-37.   D. Ernst, N. S. Kim, S. Das, S. Pant, R. Rao, T. Pham, C. Ziesler, D. Blaauw,T. Austin, K. Flautner, and T. Mudge, “Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation, in Proc. 36 th Annual IEEE/ACM International Symposium on Microarchitecture, Dec. 2003, pp. 7-18.

31. Dec 3, 2008Sheth: MS Thesis31 Thank You !!