1. 1 ENGG 1203 Tutorial Combinational Logic (II) and Sequential Logic (I) 8 Feb Learning Objectives  Apply Karnaugh map for logic simplification  Design a finite state machine News  HW1 (Feb 22, 2013, 11:55pm) Ack.: HKU ELEC1008, ISU CprE 281x, PSU CMPEN270, Wikipedia

2. 2 Simplify the Boolean expression of the circuit Change each NAND gate in the circuit to a NOR gate, and simplify the Boolean expression of the circuit Simplification using K-map

3. 3 MNQx 0000 0010 0100 0111 1000 1011 1100 1111 01101 01000 10110100 NQ M From truth table to K-map Solution (a)

4. 4 MNQx 0000 0011 0100 0111 1000 1011 1101 1111 11101 01100 10110100 NQ M Solution (b)

5. Finite State Machine (FSM) State transition diagram  Truth table  K-Map  Circuit State  Present state: before the register  Next state: after the register  State transition: during clock  2 n states: n FFs 5

6. Turnstile – Control access  Depositing a token in a slot on the turnstile unlocks the arms, allowing a single customer to push through.  After the customer passes through, the arms are locked again until another coin is inserted. A simple Finite State Machine (FSM) Current StateInputNext StateOutput Locked coinUnlockedRelease turnstile so customer can push through pushLockedNone Unlocked coinUnlockedNone pushLockedWhen customer has pushed through, lock turnstile 6

7. A simple FSM 7 State Transition Transition condition Arm: 0 Arm: 1 Current StateInputNext StateOutput Locked coinUnlockedRelease turnstile so customer can push through pushLockedNone Unlocked coinUnlockedNone pushLockedWhen customer has pushed through, lock turnstile Specification  FSM

8. Steps in designing a state machine Draw a state transition diagram  An initial state  Other states to keep track of various activities  Transitions Generate a state transition table and a output table  Write state transition table and output table in binary State assignment, i.e., the code used for each state Derive canonical sum-of-product expressions Draw the circuit 8

9. From state transition diagram to truth table Four states  Two-bit state q: Present state q*: Next state z: Output 9 Condition/Output

10. From truth table to K-map 10 DADA DBDB DADA DBDB AB

11. From K-map to circuit 11 Logic for state transition State registerLogic for output

12. A simple FSM design Design a state machine that will repeatedly display in binary values 1 (001), 3 (011), 5 (101), and 7 (111)  How many states we need?  S0, S1, S2, S3  Simplified state transition diagram? 12

13. Solution Output table L2 = XY'+XY = X L1 = X'Y+XY = Y L0 = X'Y'+X'Y+XY'+XY = 1 State transition table X = X'Y+XY' Y = X'Y+XY' = Y' 13 Current stateOutput S0 (00)1 (001) S1 (01)3 (011) S2 (10)5 (101) S3 (11)7 (111) CurrentOutput XYL2L1L0 00001 01011 10101 11111 Current stateNext state S0 (00)S1 (01) S2 (10) S3 (11) S0 (00) CurrentNext XYXY 0001 0110 1011 1100

14. A complicated FSM design Vending Machine  Collect money, deliver product and change Vending machine may get three inputs  Inputs are nickel (5c), dime (10c), and quarter (25c)  Only one coin input at a time  Product cost is 40c  Does not accept more than 50c  Returns 5c or 10c back  Exact change appreciated 14

15. Solution We are designing a Mealy state machine (i.e., output depends on both current state and inputs). Suppose we ask the machine to directly return the coin if it cannot accept an input coin. Input specification: I 1 I 2  Represent the coin inserted  00 - no coin (0 cent), 01 – nickel (5 cents), 10 – dime (10 cents), 11 – quarter (25 cents) Output specification: C 1 C 2 P  C 1 C 2 represent the coin returned – 00, 01, 10, 11  P indicates whether to deliver product – 0, 1 15

16. Solution States: S 1 S 2 S 3  Represent the money inside the machine now  3 bits are enough to encode the states S00 (0 cents) – 000 S05 (5 cents) – 001 S10 – 010 S15 – 011 S20 – 100 S25 – 101 S30 – 110 S35 – 111 16

17. Solution 17

18. Solution 18 S35 11/110  S35 10/011  S00 01/001  S00 11/110 11/000 01/000 10/000 S35: Currently the machine has 35 cents e.g. 11/110 : If we insert a quarter (11), then the machine should return one quarter and zero product (110)  35c (35 cents inside the machine now) + 25c (insert 25 cents) = 35c (35 cents inside the machine in the next state) + 25c (return 25 cents) + 0c (return no product) Input Output Next state 00/000  S35

19. Solution 19 S35 11/110  S35 10/011  S00 01/001  S00 11/110 11/000 01/000 10/000 e.g. 10/011: If we insert a dime (10), then the machine should return one nickel and one product (011)  35c (35 cents inside the machine now) + 10c (insert 10 cents) = 0c (zero cent inside the machine in the next state) + 5c (return 5 cents) + 40c (return one product) e.g. 01/001: If we insert a nickel (01), then the machine should return zero coin and one product (001)  35c (35 cents inside the machine now) + 5c (insert 5 cents) = 0c (zero cent inside the machine in the next state) + 0c (return zero cent) + 40c (return one product) 00/000  S35

20. 20 (Appendix) Simplification using K-map Simplify the following Boolean expressions using Karnaugh map.

21. 21 Solution A/B01 000 111 A/BC00011110 00011 11111 i) ii)

22. (Appendix) Counter Figure a) shows a complete four-bit parallel adder with registers and b) shows the signals used to add binary numbers from memory and store their sum in the accumulator. Suppose the numbers being added are 1001 and 0101. Also assume that C o =0. Describe what happen at t 1, t 2, t 3, t 4 and t 5. 22

23. Solution 23

24. 24

25. At time t 2, load is active high  Set A numbers will be loaded into the upper register At time t 3, transfer is active high  Adder process between A 3 A 2 A 1 A 0 = 0000 and B 3 B 2 B 1 B 0 = 1001 The sum S 3 S 2 S 1 S 0 = 1001 are transferred to register A on PGT due to this transfer pulse at t 3 25

26. At time t 4, the load is active high, the set B numbers will be loaded into register B on PGT of LOAD pulse  B 3 B 2 B 1 B 0 = 0101 At time t 5, A 3 A 2 A 1 A 0 = 1001 and B 3 B 2 B 1 B 0 = 0101, the adder produces S 3 S 2 S 1 S 0 = 1110. This sum is transferred into register A when TRANSFER pulse occur at t 5. 26

27. (Appendix) State changing in FSM Design a 2-bit counter with input x that can be  A down counter when x = 0 (…  11  10  01  00  11  …)  A Johnson counter when x = 1 (…  00  01  11  10  00  …) 27

28. Solution 28

29. (Appendix) A typical FSM 29 FSM  Truth table  Circuit Logic for output Logic for state transition State register