1. Computer Architecture I: Outline and Instruction Set Architecture
CENG Computer Organization
Instructors:
Murat Manguoglu (Section 1)
Erol Sahin (Section 2 & 3)
Adapted from slides of the textbook:

2. Instruction Set Architecture
Assembly Language View
Processor state
Registers, memory, …
Instructions
addq, pushq, ret, …
How instructions are encoded as bytes
Layer of Abstraction
Above: how to program machine
Processor executes instructions in a sequence
Below: what needs to be built
Use variety of tricks to make it run fast
E.g., execute multiple instructions simultaneously
ISA
Compiler OS
CPU
Design
Circuit
Chip
Layout
Application
Program

3. CISC Instruction Sets Stack-oriented instruction set
Complex Instruction Set Computer
IA32 is example
Stack-oriented instruction set
Use stack to pass arguments, save program counter
Explicit push and pop instructions
Arithmetic instructions can access memory
addq %rax, 12(%rbx,%rcx,8)
requires memory read and write
Complex address calculation
Condition codes
Set as side effect of arithmetic and logical instructions
Philosophy
Add instructions to perform “typical” programming tasks

4. RISC Instruction Sets Fewer, simpler instructions
Reduced Instruction Set Computer
Internal project at IBM, later popularized by Hennessy (Stanford) and Patterson (Berkeley)
Fewer, simpler instructions
Might take more to get given task done
Can execute them with small and fast hardware
Register-oriented instruction set
Many more (typically 32) registers
Use for arguments, return pointer, temporaries
Only load and store instructions can access memory
Similar to Y86-64 mrmovq and rmmovq
No Condition codes
Test instructions return 0/1 in register

5. MIPS Registers

6. MIPS Instruction ExamplesOp Ra Rb Rd Fn
00000
R-R
addu $3,$2,$1 # Register add: $3 = $2+$1 Op Ra Rb
Immediate
R-I
addu $3,$2, 3145 # Immediate add: $3 = $2+3145
sll $3,$2,2 # Shift left: $3 = $2 << 2
Branch Op Ra Rb
Offset
beq $3,$2,dest # Branch when $3 = $2
Load/Store Op Ra Rb
Offset
lw $3,16($2) # Load Word: $3 = M[$2+16]
sw $3,16($2) # Store Word: M[$2+16] = $3

7. CISC vs. RISC Original Debate Current Status Strong opinions!
CISC proponents---easy for compiler, fewer code bytes
RISC proponents---better for optimizing compilers, can make run fast with simple chip design
Current Status
For desktop processors, choice of ISA not a technical issue
With enough hardware, can make anything run fast
Code compatibility more important
x86-64 adopted many RISC features
More registers; use them for argument passing
For embedded processors, RISC makes sense
Smaller, cheaper, less power
Most cell phones use ARM processor

8. Y86-64 Processor State Program Registers Condition Codes
RF: Program registers
CC: Condition codes
Stat: Program status
%r8
%r9
%r10
%r11
%r12
%r13
%r14
%rax
%rcx
%rdx
%rbx
%rsp
%rbp
%rsi
%rdi ZF SF OF
DMEM: Memory PC
Program Registers
15 registers (omit %r15). Each 64 bits
Condition Codes
Single-bit flags set by arithmetic or logical instructions
ZF: Zero SF:Negative OF: Overflow
Program Counter
Indicates address of next instruction
Program Status
Indicates either normal operation or some error condition
Memory
Byte-addressable storage array
Words stored in little-endian byte order

9. Y86-64 Instruction Set #1 Byte 1 2 3 4 5 6 7 8 9 halt nop 11 2 3 4 5 6 7 8 9
halt
nop 1
cmovXX rA, rB 2 fn rA rB
irmovq V, rB 3 F rB V
rmmovq rA, D(rB) 4 rA rB D
mrmovq D(rB), rA 5 rA rB D
OPq rA, rB 6 fn rA rB
jXX Dest 7 fn
Dest
call Dest 8
Dest
ret 9
pushq rA A rA F
popq rA B rA F

10. Y86-64 Instruction Set Byte 1 2 3 4 5 6 7 8 9 halt nop 1 cmovXX rA, rB1 2 3 4 5 6 7 8 9
halt
nop 1
cmovXX rA, rB 2 fn rA rB
irmovq V, rB 3 F rB V
rmmovq rA, D(rB) 4 rA rB D
mrmovq D(rB), rA 5 rA rB D
OPq rA, rB 6 fn rA rB
jXX Dest 7 fn
Dest
call Dest 8
Dest
ret 9
pushq rA A rA F
popq rA B rA F

11. Y86-64 Instruction Set #2 Byte rrmovq 2 1 2 3 4 5 6 7 8 9 cmovle 2 1
Byte 1 2 3 4 5 6 7 8 9
cmovle 2 1
halt
cmovl 2
nop 1
cmove 2 3
cmovXX rA, rB 2 fn rA rB
cmovne 2 4
irmovq V, rB 3 F rB V
cmovge 2 5
rmmovq rA, D(rB) 4 rA rB D
cmovg 2 6
mrmovq D(rB), rA 5 rA rB D
OPq rA, rB 6 fn rA rB
jXX Dest 7 fn
Dest
call Dest 8
Dest
ret 9
pushq rA A rA F
popq rA B rA F

12. Y86-64 Instruction Set #4 Byte jmp 7 jle 1 jl 2 je 3 jne 4 jge 5 jg 6
jle 1 jl 2 je 3
jne 4
jge 5 jg 6
Byte 1 2 3 4 5 6 7 8 9
halt
nop 1
cmovXX rA, rB 2 fn rA rB
irmovq V, rB 3 F rB V
rmmovq rA, D(rB) 4 rA rB D
mrmovq D(rB), rA 5 rA rB D
OPq rA, rB 6 fn rA rB
jXX Dest 7 fn
Dest
call Dest 8
Dest
ret 9
pushq rA A rA F
popq rA B rA F

13. Y86-64 Instruction Set Byte 1 2 3 4 5 6 7 8 9 halt nop 1 cmovXX rA, rB1 2 3 4 5 6 7 8 9
halt
nop 1
cmovXX rA, rB 2 fn rA rB
irmovq V, rB 3 F rB V
addq 6
subq 1
andq 2
xorq 3
rmmovq rA, D(rB) 4 rA rB D
mrmovq D(rB), rA 5 rA rB D
OPq rA, rB 6 fn rA rB
jXX Dest 7 fn
Dest
call Dest 8
Dest
%rax
%rcx
%rdx
%rbx 1 2 3
%rsp
%rbp
%rsi
%rdi 4 5 6 7
%r8
%r9
%r10
%r11 8 9 A B
%r12
%r13
%r14
No Register C D E F
ret 9
pushq rA A rA F
popq rA B rA F

14. Move Instruction Examples
Y86-64
movq $0xabcd, %rdx
irmovq $0xabcd, %rdx
Encoding:
30 82 cd ab
movq %rsp, %rbx
rrmovq %rsp, %rbx
Encoding:
20 43
movq -12(%rbp),%rcx
mrmovq -12(%rbp),%rcx
Encoding:
50 15 f4 ff ff ff ff ff ff ff
movq %rsi,0x41c(%rsp)
rmmovq %rsi,0x41c(%rsp)
Encoding: c

15. Conditional Move Instructions
Move Unconditionally
Refer to generically as “cmovXX”
Encodings differ only by “function code”
Based on values of condition codes
Variants of rrmovq instruction
(Conditionally) copy value from source to destination register
rrmovq rA, rB 2 rA rB
Move When Less or Equal
cmovle rA, rB 2 1 rA rB
Move When Less
cmovl rA, rB 2 rA rB
Move When Equal
cmove rA, rB 2 3 rA rB
Move When Not Equal
cmovne rA, rB 2 4 rA rB
Move When Greater or Equal
cmovge rA, rB 2 5 rA rB
Move When Greater
cmovg rA, rB 2 6 rA rB

16. Computer Architecture I: Logic Design
CENG Computer Organization
Instructors:
Murat Manguoglu (Section 1)
Erol Sahin (Section 2 & 3)
Adapted from slides of the textbook:

17. Computing with Logic Gates
Outputs are Boolean functions of inputs
Respond continuously to changes in inputs
With some, small delay
Rising Delay
Falling Delay
a && b b
Voltage a
Time

18. Combinational Circuits
Acyclic Network
Primary
Inputs
Outputs
Acyclic Network of Logic Gates
Continously responds to changes on primary inputs
Primary outputs become (after some delay) Boolean functions of primary inputs

19. bool eq = (a&&b)||(!a&&!b)
Bit Equality
Bit equal a b eq
HCL Expression
bool eq = (a&&b)||(!a&&!b)
Generate 1 if a and b are equal
Hardware Control Language (HCL)
Very simple hardware description language
Boolean operations have syntax similar to C logical operations
We’ll use it to describe control logic for processors

20. Word-Level Representation
Word Equality
Word-Level Representation
b63
Bit equal
a63
eq63
b62
a62
eq62 b1 a1
eq1 b0 a0
eq0 Eq = B A Eq
HCL Representation
bool Eq = (A == B)
64-bit word size
HCL representation
Equality operation
Generates Boolean value

21. Bit-Level Multiplexors
Bit MUX
HCL Expression
bool out = (s&&a)||(!s&&b) b
out a
Control signal s
Data signals a and b
Output a when s=1, b when s=0

22. Word-Level Representation
Word Multiplexor
Word-Level Representation
b63 s
a63
out63
b62
a62
out62 b0 a0
out0 s B A
Out
MUX
HCL Representation
int Out = [
s : A;
1 : B; ];
Select input word A or B depending on control signal s
HCL representation
Case expression
Series of test : value pairs
Output value for first successful test

23. HCL Word-Level Examples
Minimum of 3 Words
Find minimum of three input words
HCL case expression
Final case guarantees match
int Min3 = [
A < B && A < C : A;
B < A && B < C : B;
: C; ]; A
Min3
MIN3 B C
4-Way Multiplexor D0 D3
Out4 s0 s1
MUX4 D2 D1
Select one of 4 inputs based on two control bits
HCL case expression
Simplify tests by assuming sequential matching
int Out4 = [
!s1&&!s0: D0;
!s1 : D1;
!s0 : D2;
: D3; ];

24. Arithmetic Logic Unit Combinational logicY X
X + Y A L U Y X
X - Y 1 A L U Y X
X & Y 2 A L U Y X
X ^ Y 3 A B A B A B A B OF ZF CF OF ZF CF OF ZF CF OF ZF CF
Combinational logic
Continuously responding to inputs
Control signal selects function computed
Corresponding to 4 arithmetic/logical operations in Y86-64
Also computes values for condition codes

25. Registers Stores word of data Collection of edge-triggered latches
Structure D C Q+ i7 i6 i5 i4 i3 i2 i1 i0 o7 o6 o5 o4 o3 o2 o1 o0
Clock I O
Clock
Stores word of data
Different from program registers seen in assembly code
Collection of edge-triggered latches
Loads input on rising edge of clock

26. Register Operation   y x Stores data bits
State = x 
State = y
Output = y y
Rising
clock  x
Input = y
Output = x
Stores data bits
For most of time acts as barrier between input and output
As clock rises, loads input

27. State Machine Example Accumulator circuit
Comb. Logic A L U
Out
MUX 1
Clock In
Load
Accumulator circuit
Load or accumulate on each cycle x0 x1 x2 x3 x4 x5
x0+x1
x0+x1+x2
x3+x4
x3+x4+x5
Clock
Load In
Out

28. Random-Access Memory Stores multiple words of memory Register fileB W
dstW
srcA
valA
srcB
valB
valW
Read ports
Write port
Clock
Stores multiple words of memory
Address input specifies which word to read or write
Register file
Holds values of program registers
%rax, %rsp, etc.
Register identifier serves as address
ID 15 (0xF) implies no read or write performed
Multiple Ports
Can read and/or write multiple words in one cycle
Each has separate address and data input/output

29. Register File Timing   Reading Writing Like combinational logic 2
Output data generated based on input address
After some delay
Writing
Like register
Update only as clock rises
Register
file A B
srcA
valA
srcB
valB 2 x x 2 y 2
Register
file W
dstW
valW
Clock x 
Register
file W
dstW
valW
Clock y 2
Rising
clock 

30. Hardware Control Language
Very simple hardware description language
Can only express limited aspects of hardware operation
Parts we want to explore and modify
Data Types
bool: Boolean
a, b, c, …
int: words
A, B, C, …
Does not specify word size---bytes, 64-bit words, …
Statements
bool a = bool-expr ;
int A = int-expr ;

31. HCL Operations Boolean Expressions Word Expressions
Classify by type of value returned
Boolean Expressions
Logic Operations
a && b, a || b, !a
Word Comparisons
A == B, A != B, A < B, A <= B, A >= B, A > B
Set Membership
A in { B, C, D }
Same as A == B || A == C || A == D
Word Expressions
Case expressions
[ a : A; b : B; c : C ]
Evaluate test expressions a, b, c, … in sequence
Return word expression A, B, C, … for first successful test

32. SEQ Hardware Structure
newPC
SEQ Hardware Structure PC
valE ,
valM
Write back
valM
State
Program counter register (PC)
Condition code register (CC)
Register File
Memories
Access same memory space
Data: for reading/writing program data
Instruction: for reading instructions
Instruction Flow
Read instruction at address specified by PC
Process through stages
Update program counter
Data
Data
Memory
memory
memory
Addr
, Data
valE CC CC
Execute
Cnd
ALU
ALU
aluA ,
aluB
valA ,
valB
Decode
srcA ,
srcB
dstA ,
dstB
Register
Register A A B B
Register
Register M M
file
file
file
file E E
icode ,
ifun
valP rA , rB
valC
Instruction
Instruction PC PC
Fetch
memory
memory
increment
increment PC

33. SEQ Stages Fetch Decode Execute Memory Write Back PC
newPC
SEQ Stages PC
valE ,
valM
Write back
valM
Fetch
Read instruction from instruction memory
Decode
Read program registers
Execute
Compute value or address
Memory
Read or write data
Write Back
Write program registers PC
Update program counter
Data
Data
Memory
memory
memory
Addr
, Data
valE CC CC
Execute
Cnd
ALU
ALU
aluA ,
aluB
valA ,
valB
Decode
srcA ,
srcB
dstA ,
dstB
Register
Register A A B B
Register
Register M M
file
file
file
file E E
icode ,
ifun
valP rA , rB
valC
Instruction
Instruction PC PC
Fetch
memory
memory
increment
increment PC

34. Instruction Decoding Instruction Format Instruction byte icode:ifun
Optional
Optional 5 rA rB D
icode
ifun rA rB
valC
Instruction Format
Instruction byte icode:ifun
Optional register byte rA:rB
Optional constant word valC

35. Executing Arith./Logical Operation
OPq rA, rB 6 fn rA rB
Fetch
Read 2 bytes
Decode
Read operand registers
Execute
Perform operation
Set condition codes
Memory
Do nothing
Write back
Update register
PC Update
Increment PC by 2

36. Stage Computation: Arith/Log. Ops
OPq rA, rB
icode:ifun  M1[PC]
rA:rB  M1[PC+1]
valP  PC+2
Fetch
Read instruction byte
Read register byte
Compute next PC
valA  R[rA]
valB  R[rB]
Decode
Read operand A
Read operand B
valE  valB OP valA
Set CC
Execute
Perform ALU operation
Set condition code register
Memory
R[rB]  valE
Write
back
Write back result
PC  valP
PC update
Update PC
Formulate instruction execution as sequence of simple steps
Use same general form for all instructions

37. Executing rmmovq Fetch Decode Execute Memory Write back PC Update 4 rB
rmmovq rA, D(rB) 4 rA rB D
Fetch
Read 10 bytes
Decode
Read operand registers
Execute
Compute effective address
Memory
Write to memory
Write back
Do nothing
PC Update
Increment PC by 10

38. Stage Computation: rmmovq
rmmovq rA, D(rB)
Fetch
icode:ifun  M1[PC]
Read instruction byte
rA:rB  M1[PC+1]
Read register byte
valC  M8[PC+2]
Read displacement D
valP  PC+10
Compute next PC
valA  R[rA]
valB  R[rB]
Decode
Read operand A
Read operand B
valE  valB + valC
Execute
Compute effective address
M8[valE]  valA
Memory
Write value to memory
Write
back
PC  valP
PC update
Update PC
Use ALU for address computation

39. Executing popq Fetch Decode Execute Memory Write back PC Update
popq rA b rA 8
Fetch
Read 2 bytes
Decode
Read stack pointer
Execute
Increment stack pointer by 8
Memory
Read from old stack pointer
Write back
Update stack pointer
Write result to register
PC Update
Increment PC by 2

40. Stage Computation: popq
popq rA
icode:ifun  M1[PC]
rA:rB  M1[PC+1]
valP  PC+2
Fetch
Read instruction byte
Read register byte
Compute next PC
valA  R[%rsp]
valB  R[%rsp]
Decode
Read stack pointer
valE  valB + 8
Execute
Increment stack pointer
valM  M8[valA]
Memory
Read from stack
R[%rsp]  valE
R[rA]  valM
Write
back
Update stack pointer
Write back result
PC  valP
PC update
Update PC
Use ALU to increment stack pointer
Must update two registers
Popped value
New stack pointer

41. Executing Conditional Moves
cmovXX rA, rB 2 fn rA rB
Fetch
Read 2 bytes
Decode
Read operand registers
Execute
If !cnd, then set destination register to 0xF
Memory
Do nothing
Write back
Update register (or not)
PC Update
Increment PC by 2

42. Stage Computation: Cond. Move
cmovXX rA, rB
icode:ifun  M1[PC]
rA:rB  M1[PC+1]
valP  PC+2
Fetch
Read instruction byte
Read register byte
Compute next PC
valA  R[rA]
valB  0
Decode
Read operand A
valE  valB + valA
If ! Cond(CC,ifun) rB  0xF
Execute
Pass valA through ALU
(Disable register update)
Memory
R[rB]  valE
Write
back
Write back result
PC  valP
PC update
Update PC
Read register rA and pass through ALU
Cancel move by setting destination register to 0xF
If condition codes & move condition indicate no move

43. Executing Jumps Fetch Decode Execute Memory Write back PC Update
jXX Dest 7 fn
Dest
Not taken
fall thru: XX
target: XX
Taken
Fetch
Read 9 bytes
Increment PC by 9
Decode
Do nothing
Execute
Determine whether to take branch based on jump condition and condition codes
Memory
Do nothing
Write back
PC Update
Set PC to Dest if branch taken or to incremented PC if not branch

44. Stage Computation: Jumps
jXX Dest
icode:ifun  M1[PC]
valC  M8[PC+1]
valP  PC+9
Fetch
Read instruction byte
Read destination address
Fall through address
Decode
Cnd  Cond(CC,ifun)
Execute
Take branch?
Memory
Write
back
PC  Cnd ? valC : valP
PC update
Update PC
Compute both addresses
Choose based on setting of condition codes and branch condition

45. Executing call Fetch Decode Execute Memory Write back PC Update
call Dest 8
Dest XX
return:
target:
Fetch
Read 9 bytes
Increment PC by 9
Decode
Read stack pointer
Execute
Decrement stack pointer by 8
Memory
Write incremented PC to new value of stack pointer
Write back
Update stack pointer
PC Update
Set PC to Dest

46. Stage Computation: call
call Dest
icode:ifun  M1[PC]
valC  M8[PC+1]
valP  PC+9
Fetch
Read instruction byte
Read destination address
Compute return point
valB  R[%rsp]
Decode
Read stack pointer
valE  valB + –8
Execute
Decrement stack pointer
M8[valE]  valP
Memory
Write return value on stack
R[%rsp]  valE
Write
back
Update stack pointer
PC  valC
PC update
Set PC to destination
Use ALU to decrement stack pointer
Store incremented PC

47. Executing ret Fetch Decode Execute Memory Write back PC Update9
return: XX
Fetch
Read 1 byte
Decode
Read stack pointer
Execute
Increment stack pointer by 8
Memory
Read return address from old stack pointer
Write back
Update stack pointer
PC Update
Set PC to return address

48. Stage Computation: ret
icode:ifun  M1[PC]
Fetch
Read instruction byte
valA  R[%rsp]
valB  R[%rsp]
Decode
Read operand stack pointer
valE  valB + 8
Execute
Increment stack pointer
valM  M8[valA]
Memory
Read return address
R[%rsp]  valE
Write
back
Update stack pointer
PC  valM
PC update
Set PC to return address
Use ALU to increment stack pointer
Read return address from memory

49. Computation Steps All instructions follow same general pattern
OPq rA, rB
Fetch
icode,ifun
icode:ifun  M1[PC]
Read instruction byte
rA,rB
rA:rB  M1[PC+1]
Read register byte
valC
[Read constant word]
valP
valP  PC+2
Compute next PC
Decode
valA, srcA
valA  R[rA]
Read operand A
valB, srcB
valB  R[rB]
Read operand B
Execute
valE
valE  valB OP valA
Perform ALU operation
Cond code
Set CC
Set/use cond. code reg
Memory
valM
[Memory read/write]
Write
back
dstE
R[rB]  valE
Write back ALU result
dstM
[Write back memory result]
PC update PC
PC  valP
Update PC
All instructions follow same general pattern
Differ in what gets computed on each step

50. Computation Steps All instructions follow same general pattern
call Dest
Fetch
icode,ifun
icode:ifun  M1[PC]
Read instruction byte
rA,rB
[Read register byte]
valC
valC  M8[PC+1]
Read constant word
valP
valP  PC+9
Compute next PC
Decode
valA, srcA
[Read operand A]
valB, srcB
valB  R[%rsp]
Read operand B
Execute
valE
valE  valB + –8
Perform ALU operation
Cond code
[Set /use cond. code reg]
Memory
valM
M8[valE]  valP
Memory read/write
Write
back
dstE
R[%rsp]  valE
Write back ALU result
dstM
[Write back memory result]
PC update PC
PC  valC
Update PC
All instructions follow same general pattern
Differ in what gets computed on each step

51. Computed Values Fetch Decode Execute Memory icode Instruction code
ifun Instruction function
rA Instr. Register A
rB Instr. Register B
valC Instruction constant
valP Incremented PC
Decode
srcA Register ID A
srcB Register ID B
dstE Destination Register E
dstM Destination Register M
valA Register value A
valB Register value B
Execute
valE ALU result
Cnd Branch/move flag
Memory
valM Value from memory

52. SEQ Hardware Key Blue boxes: predesigned hardware blocks
E.g., memories, ALU
Gray boxes: control logic
Describe in HCL
White ovals: labels for signals
Thick lines: bit word values
Thin lines: bit values
Dotted lines: bit values

53. Fetch Logic Predefined Blocks PC: Register containing PC
Instruction
memory PC
increment rB
icode
ifun rA
valC
valP
Need
regids
Instr
valid
Align
Split
Bytes 1-9
Byte 0
imem_error
Predefined Blocks
PC: Register containing PC
Instruction memory: Read 10 bytes (PC to PC+9)
Signal invalid address
Split: Divide instruction byte into icode and ifun
Align: Get fields for rA, rB, and valC

54. Fetch Logic Control Logic Instr. Valid: Is this instruction valid?
memory PC
increment rB
icode
ifun rA
valC
valP
Need
regids
Instr
valid
Align
Split
Bytes 1-9
Byte 0
imem_error
Control Logic
Instr. Valid: Is this instruction valid?
icode, ifun: Generate no-op if invalid address
Need regids: Does this instruction have a register byte?
Need valC: Does this instruction have a constant word?

55. Fetch Control Logic in HCL
Instruction
memory PC
Split
Byte 0
imem_error
icode
ifun
# Determine instruction code
int icode = [
imem_error: INOP;
1: imem_icode; ];
# Determine instruction function
int ifun = [
imem_error: FNONE;
1: imem_ifun;

56. Fetch Control Logic in HCL
popq rA A rA F
jXX Dest 7 fn
Dest B
call Dest 8
cmovXX rA, rB 2 rB
irmovq V, rB 3 V
rmmovq rA, D(rB) 4 D
mrmovq D(rB), rA 5
OPq rA, rB 6
ret 9
nop 1
halt
bool need_regids =
icode in { IRRMOVQ, IOPQ, IPUSHQ, IPOPQ,
IIRMOVQ, IRMMOVQ, IMRMOVQ };
bool instr_valid = icode in
{ INOP, IHALT, IRRMOVQ, IIRMOVQ, IRMMOVQ, IMRMOVQ,
IOPQ, IJXX, ICALL, IRET, IPUSHQ, IPOPQ };

57. Decode Logic Register File Control Logic Signals Read ports A, B
Write ports E, M
Addresses are register IDs or 15 (0xF) (no access) rB
dstE
dstM
srcA
srcB
Register
file A B M E
icode rA
valB
valA
valE
valM
Cnd
Control Logic
srcA, srcB: read port addresses
dstE, dstM: write port addresses
Signals
Cnd: Indicate whether or not to perform conditional move
Computed in Execute stage

58. A Source cmovXX rA, rB valA  R[rA] Decode Read operand A
rmmovq rA, D(rB)
popq rA
valA  R[%rsp]
Read stack pointer
jXX Dest
No operand
call Dest
ret
OPq rA, rB
A Source
int srcA = [
icode in { IRRMOVQ, IRMMOVQ, IOPQ, IPUSHQ } : rA;
icode in { IPOPQ, IRET } : RRSP;
1 : RNONE; # Don't need register ];

59. E Desti- nation None R[%rsp]  valE Update stack pointer R[rB]  valE
cmovXX rA, rB
Write-back
rmmovq rA, D(rB)
popq rA
jXX Dest
call Dest
ret
Conditionally write back result
OPq rA, rB
Write back result
E Desti- nation
int dstE = [
icode in { IRRMOVQ } && Cnd : rB;
icode in { IIRMOVQ, IOPQ} : rB;
icode in { IPUSHQ, IPOPQ, ICALL, IRET } : RRSP;
1 : RNONE; # Don't write any register ];

60. Execute Logic Units Control Logic ALU CC cond cond
Implements 4 required functions
Generates condition code values CC
Register with 3 condition code bits
cond
Computes conditional jump/move flag
Control Logic
Set CC: Should condition code register be loaded?
ALU A: Input A to ALU
ALU B: Input B to ALU
ALU fun: What function should ALU compute? CC
ALU A B
fun.
Cnd
icode
ifun
valC
valB
valA
valE
Set
cond

61. ALU A Input int aluA = [ icode in { IRRMOVQ, IOPQ } : valA;
valE  valB + –8
Decrement stack pointer
No operation
valE  valB + 8
Increment stack pointer
valE  valB + valC
Compute effective address
valE  0 + valA
Pass valA through ALU
cmovXX rA, rB
Execute
rmmovq rA, D(rB)
popq rA
jXX Dest
call Dest
ret
valE  valB OP valA
Perform ALU operation
OPq rA, rB
int aluA = [
icode in { IRRMOVQ, IOPQ } : valA;
icode in { IIRMOVQ, IRMMOVQ, IMRMOVQ } : valC;
icode in { ICALL, IPUSHQ } : -8;
icode in { IRET, IPOPQ } : 8;
# Other instructions don't need ALU ];

62. ALU Oper- ation valE  valB + –8 Decrement stack pointer No operation
Increment stack pointer
valE  valB + valC
Compute effective address
valE  0 + valA
Pass valA through ALU
cmovXX rA, rB
Execute
rmmovl rA, D(rB)
popq rA
jXX Dest
call Dest
ret
valE  valB OP valA
Perform ALU operation
OPl rA, rB
ALU Oper- ation
int alufun = [
icode == IOPQ : ifun;
1 : ALUADD; ];

63. Memory Logic Memory Control Logic Reads or writes memory word
Data
memory
Mem.
read
addr
write
data out
data
valE
valM
valA
valP
data in
icode
Stat
dmem_error
instr_valid
imem_error
stat
Memory
Reads or writes memory word
Control Logic
stat: What is instruction status?
Mem. read: should word be read?
Mem. write: should word be written?
Mem. addr.: Select address
Mem. data.: Select data

64. Instruction Status Control Logic stat: What is instruction status?
Data
memory
Mem.
read
addr
write
data out
data
valE
valM
valA
valP
data in
icode
Stat
dmem_error
instr_valid
imem_error
stat
Control Logic
stat: What is instruction status?
## Determine instruction status
int Stat = [
imem_error || dmem_error : SADR;
!instr_valid: SINS;
icode == IHALT : SHLT;
1 : SAOK; ];

65. Memory Address OPq rA, rB Memory rmmovq rA, D(rB) popq rA jXX Dest
call Dest
ret
No operation
M8[valE]  valA
Write value to memory
valM  M8[valA]
Read from stack
M8[valE]  valP
Write return value on stack
Read return address
int mem_addr = [
icode in { IRMMOVQ, IPUSHQ, ICALL, IMRMOVQ } : valE;
icode in { IPOPQ, IRET } : valA;
# Other instructions don't need address ];

66. Memory Read OPq rA, rB Memory rmmovq rA, D(rB) popq rA jXX Dest
call Dest
ret
No operation
M8[valE]  valA
Write value to memory
valM  M8[valA]
Read from stack
M8[valE]  valP
Write return value on stack
Read return address
bool mem_read = icode in { IMRMOVQ, IPOPQ, IRET };

67. PC Update Logic New PC Select next value of PC New PC Cnd icode valC
valP
valM
New PC
Select next value of PC

68. PC Update OPq rA, rB rmmovq rA, D(rB) popq rA jXX Dest call Dest ret
PC  valP
PC update
Update PC
PC  Cnd ? valC : valP
PC  valC
Set PC to destination
PC  valM
Set PC to return address
int new_pc = [
icode == ICALL : valC;
icode == IJXX && Cnd : valC;
icode == IRET : valM;
1 : valP; ];

69. SEQ Operation State Combinational Logic PC register
Cond. Code register
Data memory
Register file
All updated as clock rises
Combinational Logic
ALU
Control logic
Memory reads
Instruction memory
Combinational
logic
Data
memory
Register
file
%rbx = 0x100 PC
0x014 CC
100
Read
ports
Write

70. SEQ Operation #2 state set according to second irmovq instruction
0x014: addq %rdx,%rbx # %rbx <-- 0x300 CC <-- 000
0x016: je dest # Not taken
0x01f: rmmovq %rbx,0(%rdx) # M[0x200] <-- 0x300
Cycle 3:
Cycle 4:
Cycle 5:
0x00a: irmovq $0x200,%rdx # %rdx <-- 0x200
Cycle 2:
0x000: irmovq $0x100,%rbx # %rbx <-- 0x100
Cycle 1:
Clock
Cycle 1 j l m k
Cycle 2
Cycle 3
Cycle 4
SEQ Operation #2
Combinational
logic
Data
memory
Register
file
%rbx = 0x100 PC
0x014 CC
100
Read
ports
Write
state set according to second irmovq instruction
combinational logic starting to react to state changes

71. SEQ Operation #3 state set according to second irmovq instruction
0x014: addq %rdx,%rbx # %rbx <-- 0x300 CC <-- 000
0x016: je dest # Not taken
0x01f: rmmovq %rbx,0(%rdx) # M[0x200] <-- 0x300
Cycle 3:
Cycle 4:
Cycle 5:
0x00a: irmovq $0x200,%rdx # %rdx <-- 0x200
Cycle 2:
0x000: irmovq $0x100,%rbx # %rbx <-- 0x100
Cycle 1:
Clock
Cycle 1 j l m k
Cycle 2
Cycle 3
Cycle 4
SEQ Operation #3
Combinational
logic
Data
memory
Register
file
%rbx = 0x100 PC
0x014 CC
100
Read
ports
Write
0x016
000
%rbx
<--
0x300
state set according to second irmovq instruction
combinational logic generates results for addq instruction
Combinational
logic
Data
memory
Register
file
%rbx = 0x300 PC
0x016 CC
000
Read
ports
Write
Combinational
logic
Data
memory
Register
file
%rbx = 0x300 PC
0x016 CC
000
Read
ports
Write
Combinational
logic
Data
memory
Register
file
%rbx = 0x300 PC
0x016 CC
000
Read
ports
Write
Combinational
logic
Data
memory
Register
file
%rbx = 0x300 PC
0x016 CC
000
Read
ports
Write
Combinational
logic
Data
memory
Register
file
%rbx = 0x300 PC
0x016 CC
000
Read
ports
Write
Combinational
logic
Data
memory
Register
file
%rbx = 0x300 PC
0x016 CC
000
Read
ports
Write
Combinational
logic
Data
memory
Register
file
%rbx = 0x300 PC
0x016 CC
000
Read
ports
Write
Combinational
logic
Data
memory
Register
file
%rbx = 0x300 PC
0x016 CC
000
Read
ports
Write
Combinational
logic
Data
memory
Register
file
%rbx = 0x300 PC
0x016 CC
000
Read
ports
Write

72. SEQ Operation #4 state set according to addq instruction
0x014: addq %rdx,%rbx # %rbx <-- 0x300 CC <-- 000
0x016: je dest # Not taken
0x01f: rmmovq %rbx,0(%rdx) # M[0x200] <-- 0x300
Cycle 3:
Cycle 4:
Cycle 5:
0x00a: irmovq $0x200,%rdx # %rdx <-- 0x200
Cycle 2:
0x000: irmovq $0x100,%rbx # %rbx <-- 0x100
Cycle 1:
Clock
Cycle 1 j l m k
Cycle 2
Cycle 3
Cycle 4
SEQ Operation #4
Combinational
logic
Data
memory
Register
file
%rbx = 0x300 PC
0x016 CC
000
Read
ports
Write
state set according to addq instruction
combinational logic starting to react to state changes
Combinational
logic
Data
memory
Register
file
%rbx = 0x300 PC
0x016 CC
000
Read
ports
Write
Combinational
logic
Data
memory
Register
file
%rbx = 0x300 PC
0x016 CC
000
Read
ports
Write
Combinational
logic
Data
memory
Register
file
%rbx = 0x300 PC
0x016 CC
000
Read
ports
Write
Combinational
logic
Data
memory
Register
file
%rbx = 0x300 PC
0x016 CC
000
Read
ports
Write

73. SEQ Operation #5 state set according to addq instruction
0x014: addq %rdx,%rbx # %rbx <-- 0x300 CC <-- 000
0x016: je dest # Not taken
0x01f: rmmovq %rbx,0(%rdx) # M[0x200] <-- 0x300
Cycle 3:
Cycle 4:
Cycle 5:
0x00a: irmovq $0x200,%rdx # %rdx <-- 0x200
Cycle 2:
0x000: irmovq $0x100,%rbx # %rbx <-- 0x100
Cycle 1:
Clock
Cycle 1 j l m k
Cycle 2
Cycle 3
Cycle 4
SEQ Operation #5
Combinational
logic
Data
memory
Register
file
%rbx = 0x300 PC
0x016 CC
000
Read
ports
Write
0x01f
state set according to addq instruction
combinational logic generates results for je instruction
Combinational
logic
Data
memory
Register
file
%rbx = 0x300 PC
0x016 CC
000
Read
ports
Write
0x01f
Combinational
logic
Data
memory
Register
file
%rbx = 0x300 PC
0x016 CC
000
Read
ports
Write
0x01f
Combinational
logic
Data
memory
Register
file
%rbx = 0x300 PC
0x016 CC
000
Read
ports
Write
0x01f

74. SEQ Summary Implementation Limitations
Express every instruction as series of simple steps
Follow same general flow for each instruction type
Assemble registers, memories, predesigned combinational blocks
Connect with control logic
Limitations
Too slow to be practical
In one cycle, must propagate through instruction memory, register file, ALU, and data memory
Would need to run clock very slowly
Hardware units only active for fraction of clock cycle