1. Lev Finkelstein ISCA/Thermal Workshop 6/2004 1 Overview 1.Motivation (Kevin) 2.Thermal issues (Kevin) 3.Power modeling (David) 4.Thermal management (David) 5.Optimal DTM (Lev) 6.Clustering (Antonio) 7.Power distribution (David) 8.What current chips do (Lev) 9.HotSpot (Kevin)

2. Lev Finkelstein ISCA/Thermal Workshop 6/2004 2 What current chips do Power and thermal management

3. Lev Finkelstein ISCA/Thermal Workshop 6/2004 3 Controllers Inputs (power, temperature, etc.) Response time Tuning Simplicity of implementation Performance, reliability Power management / thermal management

4. Lev Finkelstein ISCA/Thermal Workshop 6/2004 4 Controllers (cont’d) A non-trivial tradeoff PerformanceReliability Cost

5. Lev Finkelstein ISCA/Thermal Workshop 6/2004 5 Real processors: IBM* PowerPC* G3/G4 Cache throttling AMD* PowerNow!* Technology Transmeta* Longrun* technology Intel® SpeedStep® technology Enhanced Intel® SpeedStep technology * Other names and brands may be claimed as the property of others

6. Lev Finkelstein ISCA/Thermal Workshop 6/2004 6 PowerPC G3 Microprocessor On-chip temperature sensor (junction temperature) –Based on differential voltage change across 2 diodes of different sizes –Implemented in PowerPC G3/G4 processors OS required for control Instruction Cache Throttling used to dynamically lower junction temperature From Micro-35 tutorial

7. Lev Finkelstein ISCA/Thermal Workshop 6/2004 7 Transmeta LongRun ** LongRun power management –Code Morphing* software (processor- internal) –Performance demands are determined by sampling the idle time Crusoe * processor *** –Voltage changes in steps of 25 mV –Frequency changes in steps of 33 MHz *Other names and brands may be claimed as the property of others ** Source: http://www.transmeta.comhttp://www.transmeta.com *** Data dated 2001

8. Lev Finkelstein ISCA/Thermal Workshop 6/2004 8 Transmeta LongRun (cont’d) Idle time  decrement V&f Activity  increment V&f (if possible) Performance mode  V&f adjustment Source: http://www.transmeta.com/crusoe/longrun.html

9. Lev Finkelstein ISCA/Thermal Workshop 6/2004 9 Previous Intel microprocessors 1 Thermal monitor mechanism A two-point mechanism using voltage scaling (for battery life) 1 Information on Intel microprocessors is based on Efraim Rotem’s presentation in the TACS workshop 06/2004

10. Lev Finkelstein ISCA/Thermal Workshop 6/2004 10 Thermal monitor Based on clock throttling Full operational mode: maximal frequency Minimal operation mode: clocks are stalled for a part of the duty cycle Activation options: –By OS (e.g., ACPI) –By a special hardware

11. Lev Finkelstein ISCA/Thermal Workshop 6/2004 11 Static voltage scaling (for battery life) Performance mode –Maximal frequency & Vcc –AC outlet or set by user Power saving mode –Low frequency & Vcc –Upon request or while the user changed the usage mode

12. Lev Finkelstein ISCA/Thermal Workshop 6/2004 12 The Intel Pentium® M Processor Targets the mobile market Improved power efficiency Advanced ACPI interface Enhanced SpeedStep architecture

13. Lev Finkelstein ISCA/Thermal Workshop 6/2004 13 DVS in the Pentium M Processor Changes both voltage and frequency at the runtime Efficiently switches between different DVS control points

14. Lev Finkelstein ISCA/Thermal Workshop 6/2004 14 Thermal sensors Two thermal sensors Maximal temperature reached  throttling Critical shutdown point reached  shutdown

15. Lev Finkelstein ISCA/Thermal Workshop 6/2004 15 Operation modes Software control mechanism (e.g., ACPI) –Track the junction temperature –Initiate the appropriate policy Self throttle –Digital temperature detector initiates one of the power control cycles –Used as a fail-safe mechanism since it is much faster than the software

16. Lev Finkelstein ISCA/Thermal Workshop 6/2004 16 Enhanced Intel SpeedStep technology Implements DVS Upon a thermal trigger or SW request, CPU halts execution and locks PLL at a new frequency (a few  sec) Once finished, the Vcc starts changing to the new value (order of 1mV/  sec) Transition up is done in the reverse order

17. Lev Finkelstein ISCA/Thermal Workshop 6/2004 17 DVS cycle

18. Lev Finkelstein ISCA/Thermal Workshop 6/2004 18 DVS transitions Frequency transition is fast enough to allow non-interrupted application execution DVS transitions can be utilized for energy and thermal control during the normal operation flow The target frequency and voltage are programmable by BIOS or OS Support for multiple voltage/ frequency points

19. Lev Finkelstein ISCA/Thermal Workshop 6/2004 19 Adaptive policy (for battery life) Uninterrupted power state transition User selectable policy Increases frequency on demand, and decreases power and frequency while idle for a long time

20. Lev Finkelstein ISCA/Thermal Workshop 6/2004 20 Info More specific information on Pentium M will be available at Efraim Rotem’s presentation in the TACS workshop 06/2004

21. Lev Finkelstein ISCA/Thermal Workshop 6/2004 21 ACPI and OSPM 1 ACPI = Advanced Configuration and Power Interface (an open industry specification) OSPM = Operating System-directed configuration and Power Management Cooling decisions are based on the application load and the thermal heuristics of the system 1 Source: The ACPI specification 2.0, see http://www.acpi.info/

22. Lev Finkelstein ISCA/Thermal Workshop 6/2004 22 Cooling policies Active cooling – a direct action by OSPM (e.g., turning on a fan) Passive cooling – reducing the power consumption (e.g., throttling) Critical trip points – shutdown

23. Lev Finkelstein ISCA/Thermal Workshop 6/2004 23 Example of SW-based clock throttling  P[%] = _TC1 * (T n – T n-1 ) + _TC2 * (T n –T t ) T n – current temperature T t – target temperature P n = P n-1 + HW[-  P] Pn is in % The coefficients are set by the OEM