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Nanoscale Power Delivery & PI Overview The Power Integrity (PI) Wall PI Analysis Management & Innovation Potential Publications & Discussion Raj Nair, Anasim Corp. Aug. 21, 2013 (Updated)
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08/21/13Anasim Confidential2 Power Integrity & the PI Wall 20nm SoC to 16nm FinFET transition Appears Constant Power and Constant Power Density, higher cost ~40% PI degradation; with k = 0.8 and the inverse k-root-k metric 16nm to 10nm Scale factor 0.625, leads to > 2X (> 100%) degradation in PI!! We have seen PI-related product failures (FMAX, INRUSH I) in the past and the present. Business as usual NOT an option. PI degradation with scaling* ~= For constant power density (CPD) or constant power (CP) scaling, where k is the process scaling factor, typically 0.7 Classical CPD/CP scaling → ~70% degradation in PI * “Power Integrity Analysis and Management for ICs”, Prentice-Hall, May 2010
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08/21/13Anasim Confidential3 PI analysis prior art (Droop, IR Drop) Lumped and Polygonal Not True-Physical and Spatio-Temporal, eliminates spatial variance and temporal coincidence Not wideband, and leads to pessimistic, non-optimal chip/pkg/board design. Loses local resonances, constructive/destructive noise interference
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08/21/13Anasim Confidential4 Differential ¹ modeling & design Grids, transmission lines/planes Abstract, system level, continuous² No freq/time domain discontinuities ² “Power Integrity Analysis and Management for ICs”, Prentice-Hall, May 2010 ¹ Integrity learning from the SI world and from fundamentals
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08/21/13Anasim Confidential5 PI: How do droops REALLY look? Supply differential True-physical power grid noise (π-fp); droops and propagationπ-fp
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08/21/13Anasim Confidential6 Continuum ³ analysis insight True-physical noise wave propagation (rlcsim)rlcsim ³ “Power Delivery, Integrity Analysis and Management for SoC's”, SoC 2007, FIPower Delivery, Integrity Analysis and Management for SoC's
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08/21/13Anasim Confidential7 PI mngmnt: Fundamental methods 1 nS A 100 1 nS V 1 V= 50mV VCC On-die capacitance Quantity Type (fixed/variable) Degradation in deep nanoscale (Q, leak) Placement and distribution ~130nm process Can a fine-grain distribution of de-coupling capacitors minimize the di/dt problem?
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08/21/13Anasim Confidential8 PI management: Power Grid Design Differential grid architecture Novel simulation algo. & IP* What-if analysis in minutes... * “Power Integrity Analysis and Management for ICs”, Prentice-Hall, May 2010
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08/21/13Anasim Confidential9 PI management: Power Grid Sims Anasim Corp., Power Integrity Aware Methodology Power Integrity Aware Methodology
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08/21/13Anasim Confidential10 PI Management: Package Cap Loop-L 4 4 “Power Delivery, Integrity Analysis and Management for SoC's”, SoC 2007, FIPower Delivery, Integrity Analysis and Management for SoC's Load-shift induced noise Transient & DC Package dependency Scaling challenge Exponent of scale factor Pkg. caps help, but...
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08/21/13Anasim Confidential11 PI management: Fast Regulation Simulation (0.18 μ m) Idealized parasitics 4:1 ESL ratio between grids Capacitance evenly distributed N-Series - Pass Inherently stable Fast response Charge Valve benefits ~25% VCC droop reduction in sim Apparently kicks in within 50pS LVDCAP and HVDCAP were 5pF each in the active configuration and 10pF, 0pF in the inactive mode. 65mV droop 88mV droop Sub-50pS response Raj Nair, “Distributed charge Valves”, research conducted in late 1999 at Intel Labs, Oregon
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08/21/13Anasim Confidential12 PI mngmnt: Active Noise Regulation* *Raj Nair, “Active Noise Regulators”, US Patent 7291896,http://www.anasim.com/active-noise-regulation/http://www.anasim.com/active-noise-regulation/ Tested in lumped (b/w) and continuum (π-fp) model simulationsπ-fp
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08/21/13Anasim Confidential13 Distributed Local Voltage Regulation 5 5 “Power Delivery, Integrity Analysis and Management for SoC's”, SoC 2007, FIPower Delivery, Integrity Analysis and Management for SoC's 6 Nair, US patent appl. pub. US 2005/0168890 A1, filed Jan. 24, 2004 Split, distribute lumped regulator components Switches Inductors, CAPs Reducing I L per branch Increases Bandwidth LC α (1/f 2 ) Reducing CAP need And Efficiency I 2 R losses reduced significantly (ind.) Transient-suppressing high-BW regulation 6 Modular design Flexible form factor Distributes power and heat dissipation
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08/21/13Anasim Confidential14 PI mngmnt. innovation opportunities Board, package, and chip-level Regulation, form-factor dependent Hybrid regulation Active noise regulation Distributed voltage regulation Integration (on-die, on-pkg...) Tools & Methodology (Architecture, Design, Verification...) References Power Integrity Analysis and Management for Integrated Circuits Raj Nair & Donald Bennett Prentice-Hall, Publication Date: May 17, 2010 | ISBN-10: 0137011229 | ISBN-13: 978-0137011223 | Edition: 1 http://www.amazon.com/Integrity-Analysis-Management-Integrated-Circuits/dp/0137011229/ http://www.amazon.com/Integrity-Analysis-Management-Integrated-Circuits/dp/0137011229/ Power Integrity for Nanoscale Integrated Systems Masanori Hashimoto & Raj Nair McGraw-Hill, Publication Date: February 26, 2014 | ISBN-10: 0071787763 | ISBN-13: 978-0071787765 | Edition: 1 http://www.amazon.com/Power-Integrity-Nanoscale-Integrated-Systems/dp/0071787763/ http://www.amazon.com/Power-Integrity-Nanoscale-Integrated-Systems/dp/0071787763/
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08/21/13Anasim Confidential15 Backup slides
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08/21/13Anasim Confidential16 Lumped simulation model with ANR
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08/21/13Anasim Confidential17 PRESCOTT Pre-ANR
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08/21/13Anasim Confidential18 PRESCOTT Post-ANR
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