1. MOLLER DAQ Aug 2015 meeting Team : R. Michaels, P. M. King, M. Gericke, K. Kumar R. Michaels, MOLLER Meeting, Aug, 2015

2. Overview of DAQ System Two separate DAQs, some signals (e.g. detectors) go to both. 1.Production mode integrates over helicity period 2.Counting mode for tracking studies and Q 2 Also: test stands for detectors, beamline, DAQ development, etc Trigger Supervisor (CODA) Detector VME Injector VME Beamline VME Online Farm / Event builder Tape Silo CODA Configs: crates alone or in groups expect ~6 crates ~ 1000 TByte 1 cpu Event Building 50 cpu online analysis 50 TB volatile disk 20 TB staging disk

3. DAQ Requirements Production mode zero deadtime at 2 kHz rate (helicity reversals) 600 - 800 ADC channels, 5 MB/sec/crate x 6 crates Negligible contribution to noise (<< 200 ppm counting stats per azimuthal sector )  Similar to Qweak, but a higher data rate like CLAS Counting mode 10 - 300 kHz trigger, depending on mode FADCs, regular ADCs, TDCs, I/O, scalers. R. Michaels, MOLLER Meeting, Aug, 2015

4. DAQ Strategy Production mode Capitalize on experience of Qweak, HAPPEX, PREX. Need to write specification for integrating ADCs and auxiliary electronics : timing control and I-to-V converter In the meantime, test setups can use Qweak or HAPPEX DAQ elements. Counting mode Prefer to avoid Fastbus. Deploy pipelining FADCs, VETROC. Also, scalers, I/O, etc. R. Michaels, MOLLER Meeting, Aug, 2015

5. From Qweak: TRIUMF VME integrator FPGA FPGA Prog/ Debug Ports VME Module Select Switches Status LEDs VME Access Ext Clock Enb Ext Gate Enb Ext NIM Gate Ext NIM Clock DC-DC Converter Analog Filters 8 inputs ADC See proposal for specification

6. From Qweak: TRIUMF VME integrator FPGA FPGA Prog/ Debug Ports VME Module Select Switches Status LEDs VME Access Ext Clock Enb Ext Gate Enb Ext NIM Gate Ext NIM Clock DC-DC Converter Analog Filters 8 inputs ADC Good module with excellent specs May improve design with modern chips ( obsolescence ) A faster readout is likely and desired (to increase from limit of 10 boards per crate) Need engineering support and a procurement strategy (current plan: TRIUMF ) A specification should be written. DAC noise not needed (given resolution and Shot noise)

7. Data Rates, Online Computing Needs 30 Mbytes/sec total = 10x Qweak rate Need >1 Gbit/sec network, ~1000 Terabytes of tape (MSS), and 20 Tbyte staging disk. 50 cpu farm to handle online tasks Real-time helicity-correlated feedback Online checks of data quality Prompt analysis of 100% of data with full corrections R. Michaels, MOLLER Meeting, Aug, 2015

8. Present Status of Parity DAQ in Hall A Crate in Counting Room is working good for beamline checkout, but no signals plugged in Two Qweak ADCs were added (thanks Rakitha Beminiwattha) together with HAPPEX ADCs, scalers, and I/O Plan to revive I njector Crate (Qweak) – by ~November R. Michaels, MOLLER Meeting, Aug, 2015 Testing Qweak ADCs with a few-volt ramping function  ADC value Event # glitch

9. A Fast Counting-Mode DAQ for Compton, but a precursor for MOLLER needs. VETROC CTP (FPGA) Logic signals (128) Trigger JLab FADC Integrate threshold ADC channel Sample number Deployed in Hall A plan is to commission it this Fall if we have opportunity Based on JLab FADC together with scalers and I/O. VETROC -- pipelining TDC (s) whose hits form trigger in a CTP (readout at >200 kHz, trigger formed at ~1 MHz) -- VETROC under test by Scott Barcus (W&M student; advisor Todd Averett) + Bryan Moffit and Ben Raydo

10. Conclusions -- MOLLER DAQ (thanks, Paul King, for valuable inputs) Extrapolating from successful DAQ experience from JLAB PV Experiments Need integrating DAQ, counting DAQ, and small test stands Excellent Qweak ADCs and I-to-V are good baseline designs, need an updated specification and a plan (new components, engineering support, procurement strategy) Data rates ~10x Qweak: Looks manageable with anticipated hardware (VME, network, multicore PCs, tapes), but need to keep up with 100% prompt analysis ` R. Michaels, MOLLER Meeting, Aug, 2015