1. Power Network Analysis Chung-Kuan Cheng CSE Dept. University of California, San Diego 1/22/2010

2. Page  2 Agenda  Background: power distribution networks (PDN’s)  Worst-case PDN noise prediction –Motivation –Problem formulation –Proposed Algorithm –Case study  Simulation: adaptive parallel flow using discrete Fourier transform (DFT) –Motivation –Adaptive parallel flow description –Experimental results  Conclusions and future work

3. Page  3 Research on Power Distribution Networks  Analysis –Stimulus, Noise Margin, Simulation  Synthesis –VRM, Decap, ESR, Topology  Integration –Sensors, Prediction, Stability, Robustness

4. Page  4 Publication List Power Distribution Network Simulation and Analysis [1] W. Zhang and C.K. Cheng, "Incremental Power Impedance Optimization Using Vector Fitting Modeling,“ IEEE Int. Symp. on Circuits and Systems, pp. 2439-2442, 2007. [2] W. Zhang, W. Yu, L. Zhang, R. Shi, H. Peng, Z. Zhu, L. Chua-Eoan, R. Murgai, T. Shibuya, N. Ito, and C.K. Cheng, "Efficient Power Network Analysis Considering Multi-Domain Clock Gating,“ IEEE Trans on CAD, pp. 1348-1358, Sept. 2009. [3] W.P. Zhang, L. Zhang, R. Shi, H. Peng, Z. Zhu, L. Chua-Eoan, R. Murgai, T. Shibuya, N. Ito, and C.K. Cheng, "Fast Power Network Analysis with Multiple Clock Domains,“ IEEE Int. Conf. on Computer Design, pp. 456-463, 2007. [4] W.P. Zhang, Y. Zhu, W. Yu, R. Shi, H. Peng, L. Chua-Eoan, R. Murgai, T. Shibuya, N. Ito, and C.K. Cheng, "Finding the Worst Case of Voltage Violation in Multi-Domain Clock Gated Power Network with an Optimization Method“ IEEE DATE, pp. 540-547, 2008. [5] X. Hu, W. Zhao, P. Du, A.Shayan, C.K.Cheng, “An Adaptive Parallel Flow for Power Distribution Network Simulation Using Discrete Fourier Transform,” accepted by IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), 2010.

5. Page  5 Publication List Power Distribution Network Analysis and Synthesis [6] W. Zhang, Y. Zhu, W. Yu, A. Shayan, R. Wang, Z. Zhu, C.K. Cheng, "Noise Minimization During Power-Up Stage for a Multi-Domain Power Network,“ IEEE Asia and South Pacific Design Automation Conf., pp. 391-396, 2009. [7] W. Zhang, L. Zhang, A. Shayan, W. Yu, X. Hu, Z. Zhu, E. Engin, and C.K. Cheng, "On-Chip Power Network Optimization with Decoupling Capacitors and Controlled-ESRs,“ to appear at Asia and South Pacific Design Automation Conference, 2010. [8] X. Hu, W. Zhao, Y.Zhang, A.Shayan, C. Pan, A. E.Engin, and C.K. Cheng, “On the Bound of Time-Domain Power Supply Noise Based on Frequency-Domain Target Impedance,” in System Level Interconnect Prediction Workshop (SLIP), July 2009. [9] A. Shayan, X. Hu, H. Peng, W. Zhang, and C.K. Cheng, “Parallel Flow to Analyze the Impact of the Voltage Regulator Model in Nanoscale Power Distribution Network,” in 10 th International Symposium on Quality Electronic Design (ISQED), Mar. 2009.

6. Page  6 Publication List (Cont’) 3D Power Distribution Networks [10] A. Shayan, X. Hu, “Power Distribution Design for 3D Integration”, Jacob School of Engineering Research Expo, 2009 [Best Poster Award] [11] A. Shayan, X. Hu, M.l Popovich, A.E. Engin, C.K. Cheng, “Reliable 3D Stacked Power Distribution Considering Substrate Coupling”, in International Conference on Computre Design (ICCD), 2009. [12] A. Shayan, X. Hu, C.K. Cheng, “Reliability Aware Through Silicon Via Planning for Nanoscale 3D Stacked ICs,” in Design, Automation & Test in Europe Conference (DATE), 2009. [13] A. Shayan, X.g Hu, H. Peng, W. Zhang, C.K. Cheng, M. Popovich, and X. Chen, “3D Power Distribution Network Co-design for Nanoscale Stacked Silicon IC,” in 17 th Conference on Electrical Performance of Electronic Packaging (EPEP), Oct. 2008. [5] [14] W. Zhang, W. Yu, X. Hu, A.i Shayan, E. Engin, C.K. Cheng, "Predicting the Worst-Case Voltage Violation in a 3D Power Network", Proceeding of IEEE/ACM International Workshop on System Level Interconnect Prediction (SLIP), 2009. ================================================================== T.Y. Wang, C.C.P. Chen, “Theremal-ADI a Linear Time Chip-Level Dynamic Thermal-Simulation Algorithm based on Alternating Direction Implicit Method,” IEEE Trans. On VLSI, pp. 691-700, 2003.

7. Page  7 What is a power distribution network (PDN)  Power supply noise –Resistive IR drop –Inductive Ldi/dt noise [Popovich et al. 2008]

8. Page  8 PDN Roadmap V dd of high-performance microprocessors Currents of high-performance microprocessors [ITRS 2007]

9. Page  9 PDN Roadmap Target impedance [ITRS 2007]

10. Page  10 Agenda  Background: power distribution networks (PDN’s)  Worst-case PDN noise prediction –Motivation –Problem formulation –Proposed Algorithm –Case study  Simulation: adaptive parallel flow using discrete Fourier transform (DFT) –Motivation –Adaptive parallel flow description –Experimental results  Conclusions and future work

11. Page  11 Worst Case Analysis  Target Impedance vs. Worst Cases  Noise vs. Rise Time of Stimulus  Rogue Wave of Multiple Staged Network

12. Page  12 PDN Design Methodology: Target Impedance  PDN design –Objective: low power supply noise –Popular methodology: “target impedance” [Smith ’99] Implication: if the target impedance is small, then the noise will also be small

13. Page  13 Worst-Case PDN Noise Prediction: Motivation  Problems with “target impedance” design methodology –How to set the target impedance? Small target impedance may not lead to small noise –A PDN with smaller Z max may have larger noise  Time-domain design methodology: worst-case PDN noise –If the worst-case noise is smaller than the requirement, then the PDN design is safe. Straightforward and guaranteed –How to generate the worst-case PDN noise FT : Fourier transform

14. Page  14 Worst-Case PDN Noise Prediction: Related Work  At final design stages [Evmorfopoulos ’06] –Circuit design is fully or almost complete –Realistic current waveforms can be obtained by simulation –Problem: countless input patterns lead to countless current waveforms Sample the excitation space Statistically project the sample’s own worst-case excitations to their expected position in the excitation space  At early design stages [Najm ’03 ’05 ’07 ’08 ’09] –Real current information is not available –“Current constraint” concept –Vectorless approach: no simulation needed –Problem: assume ideal current with zero transition time

15. Page  15 Ideal Worst-Case PDN Noise  Problem formulation I  PDN noise:  Worst-case current [Xiang ’09]: Zero current transition time. Unrealistic!

16. Page  16 Worst-Case Noise with Non-zero Current Transition Times  Problem formulation II T: chosen to be such that h(t) has died down to some negligible value. * f(t) replaces i(T-τ)

17. Page  17 Proposed Algorithm Based on Dynamic Programming  GetTransPos(j,k 1,k 2 ): find the smallest i such that F j (k 1,i)≤ F j (k 2,i)  Q.GetMin(): return the minimum element in the priority queue Q  Q.DeleteMin(): delete the minimum element in the priority queue Q  Q.Add(e): insert the element e in the priority queue Q

18. Page  18 Proposed Algorithm: Initial Setup  Divide the time range [0, T] into m intervals [t 0 =0, t 1 ], [t 1, t 2 ], …, [t m-1, t m =T]. h(t i ) = 0, i=1, 2, …, m-1  u 0 = 0, u 1, u 2, …, u n = b are a set of n+1 values within [0, b]. The value of f(t) is chosen from those values. A larger n gives more accurate results. h(t)

19. Page  19 Proposed Algorithm: f(t) within a time interval [ t j, t j+1 ]  I j (k,i) : worst-case f(t) starting with u k at time t j and ending with u i at time t j+1 h(t) Theorem 1: The worst-case f(t) can be cons- tructed by determining the values at the zero- crossing points of the h(t)

20. Page  20 Proposed Algorithm: Dynamic Programming Formulation  Define V j (k,i) : the corresponding output within time interval [t j, t j+1 ]  Define the intermediate objective function OPT(j,i) : the maximum output generated by the f(t) ending at time t j with the value u i  Recursive formula for the dynamic programming algorithm:  Time complexity:

21. Page  21 Acceleration of the Dynamic Programming Algorithm  Without loss of generality, consider the time interval [t j, t j+1 ] where h(t) is negative.  Define W j (k,i) : the absolute value of V j (k,i) : Lemma 1 : W j (k 2,i 2 )- W j (k 1,i 2 )≤ W j (k 2,i 1 )- W j (k 1,i 1 ) for any 0 ≤ k 1 < k 2 ≤ n and 0 ≤ i 1 < i 2 ≤ n

22. Page  22 Acceleration of the Dynamic Programming Algorithm  Define F j (k,i) : the candidate corresponding to k for OPT(j,i)  Accelerated algorithm: –Based on Theorem 2 –Using binary search and priority queue Theorem 2: Suppose k 1 < k 2, i 1 ∈ [0,n] and F j (k 1,i 1 )≤ F j (k 2,i 1 ), then for any i 2 > i 1, we have F j (k 1,i 2 )≤ F j (k 2,i 2 ).

23. Page  23 Case Study 1: Impedance 2.09mΩ @ 19.8KHz 1.69mΩ @ 465KHz 3.23mΩ @ 166MHz

24. Page  24 Case Study 1: Impulse Response Impulse response: 100ns~10µs Impulse response: 10µs~100µs Impulse response: 0s~100ns High frequency oscillation at the beginning with large amplitude, but dies down very quickly Mid-frequency oscillation with relatively small amplitude. Low frequency oscillation with the smallest amplitude, but lasts the longest Amplitude = 1861 Amplitude = 29 Amplitude = 0.01

25. Page  25 Case Study 1: Worst-Case Current  Current constraints: Zoom in  The worst-case current also oscillates with the three resonant frequencies which matches the impulse response.  Saw-tooth-like current waveform at large transition times

26. Page  26 Case Study 1: Worst-Case Noise Response

27. Page  27 Case Study 1: Worst-Case Noise vs. Transition Time  The worst-case noise decreases with transition times.  Previous approaches which assume zero current transition times result in pessimistic worst-case noise.

28. Page  28 Case Study 2: Impedance 224.3KHz 11.2MHz 98.1MHz 224.3KHz 10.9MHz 101.6MHz

29. Page  29 Case Study 2: Worst-Case Noise  for both cases: meaning that the worst-case noise is larger than Z max.  The worst-case noise can be larger even though its peak impedance is smaller.

30. Page  30 Case 3: “Rogue Wave” Phenomenon  Worst-case noise response: The maximum noise is formed when a long and slow oscillation followed by a short and fast oscillation.  Rogue wave: In oceanography, a large wave is formed when a long and slow wave hits a sudden quick wave. Low-frequency oscillation corresponds to the resonance of the 2 nd stage High-frequency oscillation corresponds to the resonance of the 1 st stage

31. Page  31 Case 3: “Rogue Wave” Phenomenon (Cont’) Equivalent input impedance of the 2 nd stage at high frequency

32. Page  32 Case 3: “Rogue Wave” Phenomenon (Cont’) I L2 ILIL

33. Page  33 Case 3: “Rogue Wave” Phenomenon (Cont’) V 2nd V 2nd_only

34. Page  34 Case 3: “Rogue Wave” Phenomenon (Cont’) I L2 I L1 ILIL

35. Page  35 Case 3: “Rogue Wave” Phenomenon (Cont’) I L2 I L1 ILIL Zoom in

36. Page  36 Case 3: “Rogue Wave” Phenomenon (Cont’) V 2nd V 1st -V 2nd V 1st_only

37. Page  37 Case 3: “Rogue Wave” Phenomenon (Cont’) V 2nd V 1st -V 2nd V 1st_only Zoom in

38. Page  38 Case 3: “Rogue Wave” Phenomenon (Cont’) V 2nd V 1st -V 2nd V 1st_only V 2nd_only V 1st max(V 1st )=37.34mV max(V 2nd_only ) + max(V 1st_only ) = 42.09mV ≈ max(V 1st )

39. Page  39 Agenda  Background: power distribution networks (PDN’s)  Analysis: worst-case PDN noise prediction –Motivation –Problem formulation –Proposed Algorithm –Case study  Simulation: adaptive parallel flow using discrete Fourier transform (DFT) –Motivation –Adaptive parallel flow description –Experimental results  Conclusions and future work

40. Page  40 PDN Simulation: Why Frequency Domain?  Huge PDN netlists –Time-domain simulation: serial - slow –Frequency-domain simulation: parallel – fast  Frequency dependent parasitics  Simulation results –Time-domain: voltage drops, simultaneous switching noise (SSN) – input dependent –Frequency-domain: impedance, anti-resonance peaks – input independent

41. Page  41 Transform Operations  Laplace Transform [Wanping ’07] –Input: Series of ramp functions –Output: Rational expressing via vector fitting –Choice of frequency samples  Discrete Fourier Transform (DFT) –Periodic signal assumption –Discrete frequency samples

42. Page  42 Basic DFT Simulation Flow

43. Page  43 Adaptive DFT Flow  Period[i] : the input period at each iteration  Interval[i] : the simulation time step at each iteration  FreqUpBd[i] : the upper bound of the input frequency range at each iteration  v i (t) : tentative time-domain output within the frequency range [0, FreqUpBd] at each iteration  Iteration #1: obtain the main part of the output  Iteration #2~k: capture the oscillations in the tail of the output (high, middle, and low resonant frequencies)  For each iteration #i, i=k, k-1, …, 2, subtract the captured tail from the outputs at iteration #j, j<i to eliminate the wrap-around effect

44. Page  44 Problem with Basic DFT Flow  “Wrap-around effect” requires long padding zeros at the end of the input –Periodicity nature of DFT  Small uniform time steps are needed to cover the input frequency range T2T3T4T T DFT repetition output Large number of simulation points! Correct Distorted! T Wrap-around

45. Page  45 Adaptive DFT Simulation  Basic ideas of the adaptive DFT flow: cancel out the wrap-around effect by subtracting the tail from the main part of the output –Main part of the output: obtained with small time step and small period; distorted by the wrap-around effect –Tail of the output: low frequency oscillation; can be captured with large time steps T2T3T4T - - - T CorrectDistorted Correct! Total number of simulation points is reduced significantly!

46. Page  46 Experimental Results: Test Case & Input  Test case: 3D PDN –One resonant peak in the impedance profile  Input current –Time step: ∆t = 20ps –Duration: T 0 = 16.88ns Impedance Original Input

47. Page  47 Experimental Results: Adaptive Flow Process  Iteration #1: v 1 (t) –∆t 1 =20ps –T 1 =20.48ns  Iteration #2: v 2 (t) –∆t 2 = 32∆t 1 = 640ps –T 2 = 4T 1 = 81.92ns  Final output: –Main part: –Tail: T1T1 2T 1 4T 1 3T 1 v 1 (t), ∆t 1 =20ps, T 1 =20.48ns Final output v 2 (t), ∆t 2 =640ps, T 2 =81.92ns

48. Page  48 Experimental Results: DFT Flow vs. SPICE

49. Page  49 Error Analysis: Error Caused by Wrap-around Effect Theorem 1 : Let be the initial value of the output voltage. Suppose for some, then the mean square error, i.e., is bounded by. Relative error: 2.09% Relative error: 0.12% Output comparisonError relative to SPICE

50. Page  50 Error Analysis: Error Caused by Different Interpolation Methods  SPICE: PWL interpolation  DFT: sinusoidal interpolation Output comparisonError relative to SPICE

51. Page  51 Time Complexity Analysis: Adaptive vs. Non-adaptive  Adaptive flow time complexity: –T i : simulation period at iteration #i, –∆t i : simulation time step at iteration #i,  Non-adaptive flow time complexity:

52. Page  52 Parallel Processing  Test case: 3D PDN –Case 1: 393930 nodes –Case 2: 1465206 nodes  Simulation time (case 2) –DFT flow: ~3.5 hr (w/ 1 prc) 76 sec (w/ 256 prcs) –HSPICE: ~38 hr

53. Page  53 Agenda  Background: power distribution networks (PDN’s)  Analysis: worst-case PDN noise prediction –Motivation –Problem formulation –Proposed Algorithm –Case study  Simulation: adaptive parallel flow using discrete Fourier transform (DFT) –Motivation –Adaptive parallel flow description –Experimental results  Conclusions and future work

54. Page  54 Remarks  Worst-case PDN noise prediction with non-zero current transition time –The worst-case PDN noise decreases with transition time –Small peak impedance may not lead to small worst-case noise –“Rogue wave” phenomenon  Adaptive parallel flow for PDN simulation using DFT –0.093% relative error compared to SPICE –10x speed up with single processor. –Parallel processing reduces the simulation time even more significantly

55. Page  55 Summary 1.Throughput/power (instruction/energy) 2.Throughput 2 /power (f x instruction/energy)  Power Distribution Network –VRMs, Switches, Decaps, ESRs, Topology,  Analysis –Stimulus, Noise Tolerance, Simulation  Control (smart grid) –High efficiency, Real time analysis, Stability, Reliability, Rapid recovery, and Self healing

56. Page  56