1. CHAP3: MOS Field-Effect Transistors (MOSFETs)1

2. FETs vs. BJTs Similarities: • Amplifiers • Switching devices
• Impedance matching circuits
Differences:
• FETs are voltage controlled devices. BJTs are current controlled
devices.
• FETs have a higher input impedance. BJTs have higher gains.
• FETs are less sensitive to temperature variations and are more easily integrated on ICs.
• FETs are generally more static sensitive than BJTs.
FET Types
•JFET: Junction FET
•MOSFET: Metal–Oxide–Semiconductor FET
D-MOSFET: Depletion MOSFET
E-MOSFET: Enhancement MOSFET

3. FET Operating Characteristics
JFET operation can be compared to a water spigot.
The source of water pressure is the accumulation of electrons at the negative pole of the drain-source voltage.
The drain of water is the electron deficiency (or holes) at the positive pole of the applied voltage.
The control of flow of water is the gate voltage that controls the width of the n-channel and, therefore, the flow of charges from source to
drain.
FET Operation: The Basic Idea
There are three basic operating conditions for a JFET:
• VGS = 0, VDS increasing to some positive value
• VGS < 0, VDS at some positive value
• Voltage-controlled resistor

4. FET ( Field Effect Transistor)
Few important advantages of FET over conventional Transistors
Unipolar device i. e. operation depends on only one type of charge carriers (h or e)
Voltage controlled Device (gate voltage controls drain current)
Very high input impedance ( )
Source and drain are interchangeable in most Low-frequency applications
Low Voltage Low Current Operation is possible (Low-power consumption)
Less Noisy as Compared to BJT
No minority carrier storage (Turn off is faster)
Self limiting device
Very small in size, occupies very small space in ICs
Low voltage low current operation is possible in MOSFETS
Zero temperature drift of out put is possible

5. Types of Field Effect Transistors (The Classification)
JFET
MOSFET (IGFET)
n-Channel JFET
p-Channel JFET
FET
Enhancement MOSFET
Depletion MOSFET
n-Channel EMOSFET
n-Channel DMOSFET
p-Channel DMOSFET
p-Channel EMOSFET

6. Fundamentals of FET
sedr42021_0401a.jpg
Figure Physical structure of the enhancement-type NMOS transistor: (a) perspective view; (b) cross-section. Typically L = 0.1 to 3 mm, W = 0.2 to 100 mm, and the thickness of the oxide layer (tox) is in the range of 2 to 50 nm.

7. Figure The enhancement-type NMOS transistor with a positive voltage applied to the gate. An n channel is induced at the top of the substrate beneath the gate.

8. sedr42021_0403.jpg
Figure An NMOS transistor with vGS > Vt and with a small vDS applied. The device acts as a resistance whose value is determined by vGS. Specifically, the channel conductance is proportional to vGS – Vt’ and thus iD is proportional to (vGS – Vt) vDS. Note that the depletion region is not shown (for simplicity).

9. sedr42021_0404.jpg
Figure The iD–vDS characteristics of the MOSFET in Fig. 4.3 when the voltage applied between drain and source, vDS, is kept small. The device operates as a linear resistor whose value is controlled by vGS.

10. sedr42021_0405.jpg
Figure Operation of the enhancement NMOS transistor as vDS is increased. The induced channel acquires a tapered shape, and its resistance increases as vDS is increased. Here, vGS is kept constant at a value > Vt.

11. sedr42021_0406.jpg
Figure The drain current iD versus the drain-to-source voltage vDS for an enhancement-type NMOS transistor operated with vGS > Vt.

12. sedr42021_0407.jpg
Figure: Increasing vDS causes the channel to acquire a tapered shape. Eventually, as vDS reaches vGS – Vt’ the channel is pinched off at the drain end. Increasing vDS above vGS – Vt has little effect (theoretically, no effect) on the channel’s shape.

13. Output or Drain (VD-ID) Characteristics of n-MOSFET
Figure: Circuit for drain characteristics of the n-channel JFET and its Drain characteristics.
Non-saturation (Ohmic) Region:
The drain current is given by
Saturation (or Pinchoff) Region:
Where, IDSS is the short circuit drain current, VP is the pinch off voltage

14. Application1:

15. Application2:
sedr42021_0420.jpg

16. Application3:
Figure: (a) Circuit for Example. (b) The circuit with some of the analysis details shown.
sedr42021_0423a.jpg

17. Output or Drain (VD-ID) Characteristics of n-JFET
Figure: Circuit for drain characteristics of the n-channel JFET and its Drain characteristics.
Non-saturation (Ohmic) Region:
The drain current is given by
Saturation (or Pinchoff) Region:
Where, IDSS is the short circuit drain current, VP is the pinch off voltage

18. VD-ID Characteristics of EMOS FET
Locus of pts where
Saturation or Pinch off Reg.
Figure: Typical drain characteristics of an n-channel JFET.

19. Figure: Transfer (or Mutual) Characteristics of n-Channel JFET
Transfer (Mutual) Characteristics of n-Channel JFET
IDSS
VGS (off)=VP
Figure: Transfer (or Mutual) Characteristics of n-Channel JFET

20. JFET Transfer Curve This graph shows the value of ID for a given value of VGS

21. Figure: Transfer (or Mutual) Characteristics of n-Channel FET
Transfer (Mutual) Characteristics of n-Channel FET
IDSS
VGS (off)=VP
Figure: Transfer (or Mutual) Characteristics of n-Channel FET

22. Biasing Circuits used for JFET
Just as we learned that the BJT must be biased for proper operation, the JFET also must be biased for operation point (ID, VGS, VDS)
In most cases the ideal Q-point will be at the middle of the transfer characteristic curve, which is about half of the IDSS.
3 types of DC JFET biasing configurations
Fixed bias circuit
Self bias circuit
Potential Divider bias circuit

23. Fixed-bias Use two voltage sources: VGG, VDD+
Use two voltage sources: VGG, VDD
VGG is reverse-biased at the Gate – Source (G-S) terminal, thus no current flows through RG (IG = 0). +
Vout _ +
Vin _
Fixed-bias

24. Fixed-bias.. Loop 1 All capacitors replaced with open-circuit
DC analysis
All capacitors replaced with open-circuit
Loop 1

25. Fixed-bias… 1. Input Loop By using KVL at loop 1: VGG + VGS = 0
VGS = - VGG
Replace VGS = -VGG in Shockley’s Eq. ,therefore:
2. Output loop
- VDD + IDRD + VDS = 0
VDS = VDD – IDRD
3. Then, plot graph by using Shockley’s Eq

26. Example : Fixed-bias Determine the following network: VGSQ IDQ VD VGVS

27. Solutions

28. Graphical solution for the network

29. Self-bias
Using only one voltage source

30. DC analysis of the self-bias configuration.
VGS + VRS = 0
Q point for VGS

31. Defining a point on the self-bias line.
Vgs ID
IDSS
0.3Vp
IDSS/2
0.5Vp
IDSS/4 Vp
0 mA

32. Sketching the self-bias line.

33. Example : Self-bias configuration

34. Solutions:

35. Sketching the device characteristics
Vgs ID
IDSS
0.3Vp
IDSS/2
0.5Vp
IDSS/4 Vp
0 mA

36. Sketching the self-bias line

37. Graphical Solutions: Determining the Q-point
IDQ=2.6mA
VGSQ=-2.6mV
Q-point

38. Mathematical Solutions

39. Solutions
IDQ = 2.6mA

40. Voltage-divider bias
IG=0A A

41. Redrawn network

42. Sketching the network equation for the voltage-divider configuration.

43. Effect of RS on the resulting Q-point.

44. Example : Voltage-divider bias

45. Solutions

46. Determining the Q-point for the network
IDQ=2.4mA
VGSQ=-1.8mV

47. solutions
How to get IDS, VGS and VDS for voltage-divider bias configuration by using mathematical solutions?

48. Exercise 3:

49. Drawing the self bias line

50. Determining the Q-point
IDQ=6.9mA
VGSQ=-0.35V

51. Exercise 4

52. Determining VGSQ for the network.

53. FET (n-channel) Biasing Circuits
For Fixed Bias Circuit
Applying KVL to gate circuit we get
and
Where, Vp=VGS-off & IDSS is Short ckt. IDS
For Self Bias Circuit

54. FET Biasing Circuits Count…
or Fixed Bias Ckt.

55. FET Self (or Source) Bias Circuit
This quadratic equation can be solved for VGS & IDS

56. The Potential (Voltage) Divider Bias

57. A Simple CS Amplifier and Variation in IDS with Vgs

58. FET frequency Analysis:
A common source (CS) amplifier is shown to the right.
The mid-frequency circuit is drawn as follows:
the coupling capacitors (Ci and Co) and the
bypass capacitor (CSS) are short circuits
short the DC supply voltage (superposition)
replace the FET with the hybrid-p model
The resulting mid-frequency circuit is shown below.

59. Figure: Simple NMOS amplifier circuit and Characteristics with load line.

60. Figure: Drain characteristics and load line

61. For drawing an a c equivalent circuit of Amp.
Assume all Capacitors C1, C2, Cs as short circuit elements for ac signal
Short circuit the d c supply
Replace the FET by its small signal model

62. Analysis of CS Amplifier
A C Equivalent Circuit
Simplified A C Equivalent Circuit

63. Analysis of CS Amplifier with Potential Divider Bias
This is a CS amplifier configuration therefore the
input is on the gate and the output is on the drain.

64. Application 1

65. The small signal equivalent circuit of CS Amp.

66. Application 2
sedr42021_p04075.jpg

67. Application 3
sedr42021_p04077.jpg

68. Application 4
sedr42021_p04087.jpg

69. Application 5
sedr42021_p04088a.jpg

70. Application 6
sedr42021_p04099.jpg

71. Application 7
sedr42021_p04101.jpg
Application: VIII

72. Application 8
sedr42021_p04104.jpg

73. Application 9
sedr42021_p04121a.jpg

74. FET Amplifier Configurations and Relationships:v + _ G V DD 1 SS 2
Common Drain (CD) Amplifier (also called “source follower”) L o D S
Note: The biasing circuit is the same for each amp.