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Published byDenis Matthews Modified over 9 years ago
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©These slides may be freely used, distributed, and incorporated into other works. 1 Addressing Modes For speed… we want fixed-size instructions, and they should be small. Fixed-size, so that 2 update PC is the one step PC PC + single constant value Small size, so that 1 fetch instruction can be done in a single memory access.
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©These slides may be freely used, distributed, and incorporated into other works. 2 A fixed-size of 32 bits is acceptable. add $4, $10, $21 add 41021 6555 21(<32)
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©These slides may be freely used, distributed, and incorporated into other works. 3 What about lw $16, X ? lw 16 X 6 5 32 43 (not <32) In fact, any instruction with an address is not < 32 bits.
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©These slides may be freely used, distributed, and incorporated into other works. 4 The use of addressing modes offer ways of answering the question: Where is the operand? If there is no choice of addressing mode, no bits of machine code identify addressing mode. With choice, extra bits are needed. MIPS: no choice!
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©These slides may be freely used, distributed, and incorporated into other works. 5 If machine code not fixed size, place address in instruction. An invented example, like the MIPS code: lw $16, X lw 16 X 6 5 effective address 32 Called direct addressing mode
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©These slides may be freely used, distributed, and incorporated into other works. 66 put address in a register lw $16, ($8) Address of variable effective address lw 16 8 6 5 5 16 Bits Calledregister direct (<32)
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©These slides may be freely used, distributed, and incorporated into other works. 77 Add the contents of 2 registers to form an address effective address Not on MIPS! (invented for an example) lw $16, ($8)($9) lw 16 8 9 6 5 5 5 21 Bits (<32)
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©These slides may be freely used, distributed, and incorporated into other works. 88 Use those extra 16 bits for a constant… lw $16, 24($8) 24 + Value in $8 address effective lw 16 8 24 6 5 5 16 32 bits The only addressing mode on the MIPS for load/store! Calledbase displacement
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©These slides may be freely used, distributed, and incorporated into other works. 99 If operand is in a register, effective address does not make sense, but called register addressing mode So, for the MIPS instruction add $12, $13, $8 ALL 3 operands imply a register addressing mode
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©These slides may be freely used, distributed, and incorporated into other works. 10 If an operand is in the instruction, called immediate mode addi $8, $9, -1 addi 8 9 -1 6 5 5 16 Bits effective address is the instruction’s address !
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©These slides may be freely used, distributed, and incorporated into other works. 11 Use any “extra” bits within the instruction for a constant. Use constant as an offset: offset + PC effective address 11
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©These slides may be freely used, distributed, and incorporated into other works. 12 beq $11, $14, somewhere somewhere: # another instruction here beq1114offset 655 16 offset ≈ somewhere – beq’s address called PC Relative
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©These slides may be freely used, distributed, and incorporated into other works. 13 Use any “extra” bits in the instruction to hold part of an address... on MIPS: jsomewhere somewhere: # instruction here 13
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©These slides may be freely used, distributed, and incorporated into other works. 14 jpart of addr 6 32-6 = 26 bits 32 address somewhere 26 bits goes in instruction other MSBs come from PC! 14
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©These slides may be freely used, distributed, and incorporated into other works. 15 memory **** //////// wonderful addressing mode that is not offered(!) any more... register indirect not on MIPS! Invented for an example: lw $8, (($9)) //////// $8 **** $9 @@@@@
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©These slides may be freely used, distributed, and incorporated into other works. 16 RISC Reduced Instruction Set Computer small instruction set machine code is a fixed size (and small) no choice of addressing modes (in the machine code) simple instructions 16
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©These slides may be freely used, distributed, and incorporated into other works. 17 CISC Complex Instruction Set Computer often, huge instruction set (up to 256 unique instructions!) machine code varies from one instruction to another in terms of size (example: x861 to 17 bytes!) often lots of addressing mode choice (each operand's addressing mode is specified independent of the others!) 17
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©These slides may be freely used, distributed, and incorporated into other works. 18 CISC addressing modes example VAX add13,(R4),R3 immediateregister register direct 13 + value from memory R3 machine code: add1 byte op code 1 byte (immediate) 8 bytes 32-bit 2’s comp 1 byte (reg direct, R4) 1 byte (reg, R3) 18
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