1. UConn CSE 241 1 CSE241: Instruction Level Architecture Base CPU/Memory Architecture Registers Fetch-Execute Cycle Instructions Addressing Modes

2. UConn CSE 241 2 Basic CPU Architecture CPU Control Path -instruction fetch and execution sequencing Data Path -user registers and ALU MARMDR Memory Data Bus Memory Address Bus

3. UConn CSE 241 3 CPU Divisions Control Path responsible for instruction fetch and execution sequencing responsible for operand fetch responsible for saving results Data Path contains user registers contains ALU “executes” instructions

4. UConn CSE 241 4 Control Path Registers PC Program Counter –points to the next instruction to be executed –thus, it contains a memory address MAR Memory Address Register –contains the address of the memory location for the current memory operation MDR Memory Data Register –contains the data to be written to or the data read from the memory location in the current memory operation IRInstruction Register –contains the current instruction being executed

5. UConn CSE 241 5 Memory Organization Data is stored as sequences of bits --basic grouping is the byte -- 8 bits Bytes are grouped into words --words may be 2 (older), 4 (current) or 8+ (modern) bytes long The byte is the basic unit for addressing memory. However, our life will be simplified if we adopt the word as the basic unit. The size of memory (almost always in bytes) is usually given by S = 2 p, where p = word size of machine (but this may be machine dependent)

6. UConn CSE 241 6 Memory Organization Word size = 16, memory size = 65536 (64KB) Word size = 20, memory size = 1048576 (1MB) Word size = 32, memory size = 4294967296 (4GB) Word size = 64, memory size = 1.844674407x10 19 this is ? bytes?

7. UConn CSE 241 7 Memory Organization MAR MDR 512 Recall: MAR contains the address of the memory location addressed MDR either contains data to be written to that address, or data read from that address Memory is viewed as an array of bytes. Addresses start at 0 and increase by 1 up to maximum size 0 1

8. UConn CSE 241 8 Memory operations Memory Read –Place address of memory location to be read into MAR –Issue a Memory_Read command to memory –Data read from memory is placed into MDR automatically (by control logic) Memory Write –Place address of memory location to be written to into MAR –Place data to be written into MDR –Issue Memory_Write command to memory –Data in MDR is written to memory automatically (by control logic)

9. UConn CSE 241 9 Fetch-Execute Cycle Basic machine cycle; repeats indefinitely Do until halted –Fetch instruction to be executed –(Decode instruction) –Fetch operands –Point PC to next instruction to be executed –Execute instruction –Save result operand

10. UConn CSE 241 10 Instruction Types There are 4 basic instruction types (3 basic) –Data movement instructions these move but do not alter data –ALU instructions these alter (operate upon) data –Flow of Control instructions these sequence instructions –Input-Output instructions these transfer data to and from the real world note that these may get classed as Data movement

11. UConn CSE 241 11 Operands Operands are the entities operated upon by instructions Operands may be stored in memory Operands may be stored in CPU registers Both memory and CPU registers have addresses Specifying the address of an operand in an instruction is called an addressing mode

12. UConn CSE 241 12 Instruction Types by Function (Examples) data movement –mov a,b a = b; ALU –add a,b a = a + b; sequencing –jsr label jump to the subroutine which starts at label I/O –in r5, portread from io port “port” to register 5

13. UConn CSE 241 13 Instruction Types by Operands As well as being distinguished by type, instructions can be distinguished by the number of operands they have Typically, instructions may have 3,2,1 or 0 operands 3-operand instructions are almost always instructions which implement binary operations e.g., –adda,b,c a = b + c 2-operand instructions are like 3-operand instructions, but one operand serves as both a source and a destination, e.g. –adda,b a = a+b 1-operand instructions are instructions which only require one operand –clra a = 0 0-operand instructions do not operate on operands e.g. –hlthalt the computer

14. UConn CSE 241 14 Source and Destination Operands An operand is called a source operand if –it appears on the right-hand side of an expression e.g., add a,b meaning a = a + b –b is a source operand, as is a An operand is called a destination operand if –it appears on the left-hand side of an expression e.g.,add a,b meaning a = a + b –a is a destination operand Some operands may be both source and destination operands (a above)

15. UConn CSE 241 15 Data encoding Data (strings of bits) in a machine may represent unsigned integers signed integers instructions character data floating point data abstract data etc. addresses What any particular string of bits “means” depends on how that string of bits gets interpreted The same string of bits is interpreted as an address by the MAR, an instruction by the IR, or a floating-point number by the FPU.

16. UConn CSE 241 16 Instruction Encoding An instruction must encode –the instruction itself –the (or a partial) address of its operand(s) –the addressing mode used to generate the address of its operand(s) Instructions can be encoded in –a variable number of bytes –a constant number of bytes this is machine-dependent

17. UConn CSE 241 17 Instruction-level architecture the architecture of the machine at this level consists of –the instructions and addressing modes –the user registers this is the “level” of the machine that an assembly-language programmer sees. It is the first “obvious” place where different machines can be seen to clearly differ Compare this to the “application program” architecture, as seen by (say) a C++ programmer; how different is a Pentium to a PowerPC at this level (discount the different OSs)

18. UConn CSE 241 18 Basic Addressing Modes There are five basic addressing modes –Immediate addressing the instruction contains the operand itself –Register addressing the instruction refers to a register which contains the operand –Direct addressing the instruction contains the address of the operand –Indirect addressing the instruction contains the address of the address of the operand –Indexed addressing the instruction contains a value to be added to an index register to give the address of the operand

19. UConn CSE 241 19 Simple Model Suppose we consider only 1-operand instructions Suppose each instruction occupies 2 32-bit words The first word identifies the instruction (and addressing mode) The second word gives the operand address

20. UConn CSE 241 20 Direct Addressing Before After clear 344786 97 344786 0 value in second word is direct address of operand; value in location 344786 is operand 344786 memory

21. UConn CSE 241 21 Indirect Addressing clear 344786 96 344786 96 value in second word is indirect address of operand; value in location 344786 is address of operand 344786 memory 96 -182 0 Before After

22. UConn CSE 241 22 Indexed Addressing clear indexed R3 100 R3 512 960 + =612 612 Before After

23. UConn CSE 241 23 Mixed modes? Indexed indirect? It is possible to mix addressing modes We could define an indexed indirect But note that we could have two ways of implementing this indexing before indirection indexing after indirection

24. UConn CSE 241 24 Indirect Indexed mode (preindexing) clear indexed R3 100 R3 512 96 + =612 612 96 323 96 0 this is the address of the address of the operand Before After

25. UConn CSE 241 25 Indirect Indexed Mode (postindexing) clear indexed R3 100 R3 512 + =1024 this is the address of the operand 100 1024 512 -192 512 0 Before After