1. ELE22MIC Lecture 24 Course Review 1 –Review Addressing Modes operation –Instruction Set Categories & instructions Review of Assignment 1 & 2 Assignment 3 Available ELE22MIC MICROPROCESSORS EXAM VENUE: THE ODEON - UNION BUILDING DATE: 7 November 2005 Starting At 14:00 Duration: 2:15

2. Addressing Modes From Lecture 5: Immediate Direct Extended Indexed Inherent Relative

3. Immediate Addressing Mode The data for the operation immediately follows the instruction The # symbol must be used to select immediate addressing Examples: LDAA #$42 ; Load Acc.A with the value $42 -> Machine Codes: 86 42 LDX #DEEE ; Load Index Register X with hex value DEEE -> Machine Codes CE DE EE

4. Direct Addressing Modes Direct Addressing can access an operand located in the first 256 bytes of memory, $00..$FF An 8-bit memory address specifies where: data is read from, or data is written to. Examples: –LDAA $42; AccA = Memory[$42] -> Machine Code 96 42 –STAA$FF; Memory[FF] = AccA –LDX $12; IX = Memory[$12]..[$13]

5. Extended Addressing Modes Extended Addressing uses 16-bit address to specify where: data is read from, or data is written to. Can be used for memory from 0..$FFFF Examples: –LDAA $4231; AccA = Memory[$4321] -> Machine Code B6 42 31 –STAA$2000; Memory[$2000] = AccA –LDX $1234; IX = Memory[$1234]..[$1235]

6. Indexed Addressing Modes (1) Indexed addressing always uses one of two index registers X or Y. Instruction Format: –Operation Offset, Index_Register –Offset is a positive 8-bit value ( 0..255 ) added to the contents of the index register ( X or Y ) –The value of the index register is not altered. –Addition is modulo 65536

7. Indexed Addressing Modes (2) –EXAMPLE: LDAA 42, X ; AccA = Memory[42+X] -> Machine Code A6 42 LDAA FF, X ; AccA = Memory[255+X] -> Machine Code A6 FF Offset byte is considered unsigned.

8. Inherent Addressing Modes All data for the instruction is within the CPU. ABA; A = A + B -> Machine code $1B MUL; D = A * B -> Machine code $3D NEGA ; A = -A -> Machine code $40 ABX; X = X + A -> Machine code $3A INX; X = X + 1 -> Machine code $08 SEC; CarryFlag= 1 -> Machine code$0D TAB; B = A -> Machine code $16

9. Addressing Modes Review Immediate, Direct, Extended, Indexed, Inherent, Relative LDAA 4231 -> B6 42 31 LDAA 42 -> 96 42 LDAA #42 -> 86 42 LDAA 42, X -> A6 42 BRA 2020 -> 20 1E (at $2000) ABA-> 1B No memory to memory moves w/o register

10. Instruction Set Categories From Lecture 6: ARITHMETIC BRANCH, JUMP & SUBROUTINE CALL/RETURN COMPARE DATA MOVEMENT LOGICAL

11. ARITHMETIC Instructions ADDITION, SUBTRACTION, TWOS COMPLEMENT (NEGATION), DECREMENT & INCREMENT MULTIPLY & DIVIDE ARITHMETIC/LOGICAL SHIFT/ROTATE BINARY CODED DECIMAL CLEAR (bit(s) = 0) & SET (bit(s) = 1) COMPARE & TEST CONDITION CODE MANIPULATION CONDITIONAL Branches SIGNED / UN-SIGNED NUMERIC INTERPRETATION DATA MOVEMENT Push/Pull Load/Store Register Transfer Registers Exchange Registers INTERRUPT HANDLING: LOGICAL LOGICAL AND LOGICAL EXCLUSIVE OR LOGICAL OR ONES-COMPLEMENT (NOT) MISCELLANEOUS

12. ADDITION ABAA = A + B ABXIX = IX + B ABYIY = IY + B ADCAA = A + M + CarryFlag ADCBB = B + M + CarryFlag ADDAA = A + M ADDBB = B + M ADDDD = D + M

13. SUBTRACTION SBAA = A - B SBCAA = A - M - CarryFla SBCBB = B - M - CarryFlag SUBAA = A - M SUBBB = B - M SUBDD = D - M

14. NEGATION NEGM = -M (direct, indexed, extended) NEGAA = -A BEGBB = -B TWOS COMPLEMENT –Relevent for signed numbers only, MSB indicates sign –Each bit is inverted, then –one is added.

15. DECREMENT DECM = M - 1 DECAA = A - 1 DECBB = B - 1 DESSP = SP - 1 DEXIX = IX - 1

16. INCREMENT INCM = M + 1 INCAA = A + 1 INCBB = B + 1 INSSP = SP + 1 INXIX = IX + 1 INYIY = IY + 1

17. MULTIPLY / DIVIDE MULTIPLY –MULD = A * B DIVIDE –IDIVIX = D / IX, D = D % IX (Unsigned Integer Divide) –FDIVIX = D / IX, D = D % IX (Unsigned fractional divide - Radix point assumed left of bit 15 of both operands)

18. Arithmetic/Logical Shift & Rotate

19. ARITHMETIC SHIFT LEFT: (Multiply by 2) ASLArithmetic Shift Left (M) ASLAArithmetic Shift Left (A) ASLBArithmetic Shift Left (B) ASLDArithmetic Shift Left (D) RIGHT: (Divide By 2, Sign-Extend MSBit) ASRArithmetic Shift Right (M) ASRAArithmetic Shift Right (A) ASRBArithmetic Shift Right (B)

20. LOGICAL SHIFT LEFT: (Same as ASL) LSLLogical Shift Left (M) LSLALogical Shift Left (A) LSLBLogical Shift Left (B) LSLDLogical Shift Left (D) RIGHT: (Zero Fill MSBit) LSRLogical Shift Right (M) LSRALogical Shift Right (A) LSRBLogical Shift Right (B) LSRDLogical Shift Right (D) ROTATE LEFT: (extended multiply) ROLROtate Left (M) ROLAROtate Left (A) ROLBROtate Left (B) RIGHT: (extended divide) RORROtate Right (M) RORAROtate Right (A) RORBROtate Right (B) BINARY CODED DECIMAL (BCD) DAADecimal Adjust after Addition Branch & Jump BRABranch Always BRNBranch Never JMPJump to Address JSRJump to Subroutine NOPNo OPeration ; i.e do nothing but fetch next instruction CLEAR (bit(s) = 0) & SET (bit(s) = 1) CLRM = 0 CLRAA = 0 CLRBB = 0 BCLRClear Bits (M) BSETSet Bits (M) COMPARE & TEST CONDITION CODE MANIPULATION CLCCarryFlag = 0Clear Carry Flag CLVOVerflowFlag = 0Clear Overflow Flag SECCarryFlag = 1Set Carry Flag SEVOVerflowFlag = 1Set Overflow Flag TAPCCR = A Transfer A to Condition Codes Register (CCR) TPAA = CCR Transfer CCR to A CONDITIONAL Branches BEQBranch if EQual BNEBranch if Not Equal BCCBranch if CarryFlag is Clear BCSBranch if CarryFlag is Set BRCLRBranch if bits clear BRSETBranch if bits set Branches for SIGNED NUMERIC INTERPRETATION BMI; Branch if MInus BPL; Branch if PLus BVS;Branch if oVerflow Set BVC;Branch if oVerflow Clear BLT;Branch if Less Than BGE;Branch if Greater-Than or Equal-to BLE;Branch if Less-Than or Equal-to Branches for UN-SIGNED NUMERIC INTERPRETATION BHI; Branch if HIgher than BHS;Branch if Higher or Same BLS;Branch if Lower or Same BLO;Branch if Lower DATA MOVEMENT Push - Push register value onto stack PSHAM[SP--] = A The contents of the A register is pushed onto the stack - i.e. stored into memory at the address contained in the stack pointer; then the stack pointer is decremented. –PSHBM[SP--] = B PSHXM[SP--] = IX.LOW ; M[SP--] = IX.HIGH PSHYM[SP--] = IY.LOW ; M[SP--] = IY.HIGH Pull - Pull (POP) value from stack to Register PULA; A = M[++Sp] The stack pointer is first incremented, and then Accumulator A is popped off the stack - i.e. loaded from memory where the stack pointer is pointing. PULB; B = M[++SP] PULX; X.HIGH = M[++SP] ; X.LOW = M[++SP] PULY; Y.HIGH = M[++SP] ; Y.LOW = M[++SP] Load Register LDAAA = M LDABB = M LDDD = M LDSSP = M LDXX = M LDYY = M Store Register Transfer Registers TAB; A = B TBA; B = A TSX; IX = SP + 1 TSY; IY = SP + 1 TXS; SP = IX - 1 TXY; SP = IY - 1 Exchange Registers XGDX;D IX XGDY;D IY INTERRUPT HANDLING: CLI; Clear interrupt Mask SEI; Set interrupt Mask SWI; Software Interrupt RTI; Return from Interrupt WAI; Wait for interrupt LOGICAL LOGICAL AND –ANDA; A = A & M –ANDB;B = B & M LOGICAL EXCLUSIVE OR –EORA;A = A ^ M –EORB;B = B ^ M LOGICAL OR –ORAA; A = A | M –ORAB; B = B | M ONES COMPLEMENT (NOT) –COM; M = M# –COMA; A = A# –COMB; B = B# MISCELLANEOUS STOP; Stop clocks TEST; Special test mode (different meaning to 80x86)

21. ROTATE LEFT: (extended multiply) ROLROtate Left (M) ROLAROtate Left (A) ROLBROtate Left (B) RIGHT: (extended divide) RORROtate Right (M) RORAROtate Right (A) RORBROtate Right (B)

22. CLEAR/BIT CLEAR/BIT SET –BYTE CLEAR: CLRM = 0 (direct, indexed / extended) CLRAA = 0 (Acc A) CLRBB = 0 (Acc B) –BIT CLEAR: BCLRClear Bits (M) Clears the bits that are set in the mask M, All other bits left unchanged –BIT SET: BSETSet Bits (M) Sets bits that are set in the mask M All other bits left unchanged

23. Jump (1) JUMP address (0..$FFFF, 0..$FF, offset,X) JMPJump to Address JSRJump to Subroutine RTSReTurn from Subroutine NOPNo OPeration ; i.e do nothing but fetch next instruction

24. Jump (2) JMPJump to Address –Load the specified address, into the program counter. –Functions like GOTO in C/BASIC/PASCAL. –For memory in range $100..FFFF - uses extended addressing –For memory in range $00..FF - uses direct addressing –For memory in range offset, X uses indexed addressing

25. Branch BRANCH (-128..+127) Branch BRABranch Always BRNBranch Never BSR Branch to SubRoutine –BSR - Same function as JSR but relative jump to subroutine i.e. must lie within +127..-128 bytes from next instruction. Saves one byte.

26. COMPARE & TEST CONDITION CODE MANIPULATION CLCCarryFlag = 0CLear Carry Flag CLVOVerflowFlag = 0 SECCarryFlag = 1SEt Carry Flag SEVOVerflowFlag = 1 TAPCCR = ATransfer A to CCR TPAA = CCRTransfer CCR to A CCR = Condition Codes Register

27. CONDITIONAL BRANCHES (1) CONDITIONAL Branches BEQBranch if EQual BNEBranch if Not Equal BCCBranch if Carry Flag is Clear BCSBranch if Carry Flag is Set BRCLRBRanch if bits CLeaR BRSETBRanch if bits SET

28. CONDITIONAL BRANCHES (2) SIGNED COMPARISON BMIBranch if Minus BPLBranch if PLus BVSBranch if oVerflow Set BVCBranch if oVerflow Clear BGTBranch if Greater-Than > BGEBranch if Greater-than or Equal-to >= BLEBranch if Less-than or Equal-to <= BLTBranch if Less Than <

29. CONDITIONAL BRANCHES (3) SIGNED NUMBERS Signed byte range: –-128..127 –“Byte Integer” Signed word range: –-32768..32767 –“Word Integer”

30. CONDITIONAL BRANCHES (3) UN-SIGNED COMPARISON BHIBranch if HIgher than > BHSBranch if Higher or Same>= BLSBranch if Lower or Same<= BLOBranch if Lower< Unsigned byte range: 0..255 Unsigned word range: 0..65535 (2 bytes)

31. PUSH Push - Push register value onto stack PSHAM[SP--] = A The contents of the A register is pushed onto the stack - i.e. stored into memory at the address contained in the stack pointer; then the stack pointer is decremented. PSHB M[SP--] = B PSHX M[SP--] = IX.LOW ; M[SP--] = IX.HIG PSHY M[SP--] = IY.LOW ; M[SP--] = IY.HIGH Pull - Pull (POP) value from stack to Register PULA; A = M[++Sp] The stack pointer is first incremented, and then Accumulator A is popped off the stack - i.e. loaded from memory where the stack pointer is pointing. PULB; B = M[++SP] PULX; X.HIGH = M[++SP] ; X.LOW = M[++SP] PULY; Y.HIGH = M[++SP] ; Y.LOW = M[++SP] Load Register LDAAA = M LDABB = M LDDD = M LDSSP = M LDXX = M LDYY = M Store Register Transfer Registers TAB; A = B TBA; B = A TSX; IX = SP + 1 TSY; IY = SP + 1 TXS; SP = IX - 1 TXY; SP = IY - 1 Exchange Registers XGDX;D IX XGDY;D IY INTERRUPT HANDLING: CLI; Clear interrupt Mask SEI; Set interrupt Mask SWI; Software Interrupt RTI; Return from Interrupt WAI; Wait for interrupt LOGICAL LOGICAL AND –ANDA; A = A & M –ANDB;B = B & M LOGICAL EXCLUSIVE OR –EORA;A = A ^ M –EORB;B = B ^ M LOGICAL OR –ORAA; A = A | M –ORAB; B = B | M ONES COMPLEMENT (NOT) –COM; M = M# –COMA; A = A# –COMB; B = B# MISCELLANEOUS STOP; Stop clocks TEST; Special test mode (different meaning to 80x86)

32. PULL Pull - Pull (POP) value from stack to Register PULA; A = M[++Sp] The stack pointer is first incremented, and then Accumulator A is popped off the stack - i.e. loaded from memory where the stack pointer is pointing. PULB ; B = M[++SP] PULX ; X.HIGH = M[++SP] ; X.LOW = M[++SP] PULY ; Y.HIGH = M[++SP] ; Y.LOW = M[++SP] Load Register LDAAA = M LDABB = M LDDD = M LDSSP = M LDXX = M LDYY = M Store Register Transfer Registers TAB; A = B TBA; B = A TSX; IX = SP + 1 TSY; IY = SP + 1 TXS; SP = IX - 1 TXY; SP = IY - 1 Exchange Registers XGDX;D IX XGDY;D IY INTERRUPT HANDLING: CLI; Clear interrupt Mask SEI; Set interrupt Mask SWI; Software Interrupt RTI; Return from Interrupt WAI; Wait for interrupt LOGICAL LOGICAL AND –ANDA; A = A & M –ANDB;B = B & M LOGICAL EXCLUSIVE OR –EORA;A = A ^ M –EORB;B = B ^ M LOGICAL OR –ORAA; A = A | M –ORAB; B = B | M ONES COMPLEMENT (NOT) –COM; M = M# –COMA; A = A# –COMB; B = B# MISCELLANEOUS STOP; Stop clocks TEST; Special test mode (different meaning to 80x86)

33. Load Register LDAAA = M LDABB = M LDDD = M LDSSP = M LDXX = M LDYY = M

34. Store Register STAAM = A STABM = B STSM = SP STDM = D STXM = IX STYM = IY

35. Transfer Registers TAB; A = B TBA; B = A TSX; IX = SP + 1 TSY; IY = SP + 1 TXS; SP = IX - 1 TXY; SP = IY - 1 –TSX, TSY - used for setting up a stack frame for referencing parameters passed on stack.

36. Exchange Registers Swaps 16 bit registers –XGDX;D IX –XGDY;D IY

37. INTERRUPT HANDLING: CLI; Clear interrupt Mask –disable hardware interrupts SEI; Set interrupt Mask –enable hardware interrupts SWI; Software Interrupt –used for system calls - eg BUFFALO RTI; Return from Interrupt –used at end of ISR to return WAI; Wait for interrupt –pushes interrupt stack values onto stack then waits for IRQ

38. LOGICAL (1) LOGICAL AND –ANDA; A = A & M –ANDB; B = B & M –Each bit is ANDed with the operand LOGICAL EXCLUSIVE OR –EORA; A = A ^ M –EORB; B = B ^ M –Each bit is XORed with the operand

39. LOGICAL (2) LOGICAL OR –ORAA; A = A | M –ORAB; B = B | M –Each bit is ORed with the operand ONES COMPLEMENT (NOT) –COM; M = M# –COMA; A = A# –COMB; B = B# –Each bit is inverted

40. MISCELLANEOUS STOP; Stop clocks TEST; Special test mode (different meaning to 80x86 instruction) BINARY CODED DECIMAL (BCD) DAADecimal Adjust after Addition

41. Branch BRANCH (PC + [-$80..$7F]) –Jump relative to current program counter (PC) –Used if the destination is close to the current instruction Branch BRABranch Always BRNBranch Never BSR Branch to subroutine

42. Using Subroutines - JSR JSR 16 bit address ($0..$FFFF, 0..$FF) JSRJump to Subroutine –Push next instruction address onto stack –then jump to the specified address RTSReturn from Subroutine –Pul the top item on the stack into the Instruction Pointer - effectively jumps to the address on the top of stack. This address is the value pushed by the JSR (or BSR) instruction.

43. Using Subroutines - BSR BSR relative address (PC + [-$80.. +$7F]) BSRBranch to Subroutine –Push next instruction address onto stack –then branch to the specified relative address How it works: –The program counter is incremented by 2. (as usual) –The PC of the next instruction is pushed onto the stack (so the stack contains the return address) –Then the relative displacement is added to the Program counter, and execution continues from there (i.e. within the subroutine).

44. INTERRUPTs SWI SWI; Software Interrupt –Pushes all user registers (not stack pointer) –The interrupt mask bit is set this prevent furthur interrupts being serviced immediately –Fetches the Vector Address from memory location –Jumps to the vector address from memory at FFF6..FFF7

46. Stack contents - during interrupt service routine

47. INTERRUPTs RTI/WAI RTI; Return from Interrupt WAI; Wait for interrupt

48. INTERRUPT MASKING: CLI; CLear Interrupt Mask Enable Interrupts on IRQ# line SEI; SEt Interrupt Mask Disable Servicing of Interrupts on IRQ# line Interrupt mask does not affect SWI (Software Interrupt) nor XIRQ.

49. Acknowledgments Motorola M68HC11 Reference Manual HC11 images derived from Motorola 11rm.pdf - HC11 Reference Manual