1. © 2008, Renesas Technology America, Inc., All Rights Reserved 1 Course Introduction  Purpose:  This course provides an overview of the Direct Memory Access Controller and the Interrupt Controller on the SH-2 and SH-2A families of 32-bit RISC microcontrollers, which are members of the SuperH ® series  Objectives:  Gain a basic knowledge of the features and operation of the direct memory access controller  Learn about the features and operation of the interrupt controller  Content:  27 pages  4 questions  Learning Time:  20 minutes

2. © 2008, Renesas Technology America, Inc., All Rights Reserved SuperH Peripheral Functions  Microcontrollers for embedded system applications require extensive on-chip peripherals to  Minimize system chip count  Reduce overall system cost  Facilitate small system size, etc.  Built-in peripheral functions must  Provide required capabilities  Deliver needed performance levels  Offer design flexibility  Maintain a basic commonality within product family, if possible  Offer an acceptable cost-benefit compromise, etc. SH-2 SuperH 32-bit RISC CPU SH7145 SuperH Series Microcontroller Multi-function Timer Pulse Unit Compare-Match Timer Watchdog Timer A/D Converter Bus Interface Flash Bus State Controller High-performance User Debug Interface Clock Pulse Generator RAM Data Transfer Controller Direct Memory Access Controller Interrupt Controller I/O Ports Serial Communication Interface User Break Controller Advanced User Debugger

3. © 2008, Renesas Technology America, Inc., All Rights Reserved 3 Direct Memory Access Controller  Performs data transfers between:  External devices with DACK  External memory  On-chip memory  Memory-mapped external I/O  On-chip peripheral modules  Frees the CPU from handling these data transfers  So CPU resources can be focused on computational operations Microcontroller DMAC On-chip Peripherals On-chip Memory Memory- mapped I/O External Devices with DACK External Memory SuperH CPU

4. © 2008, Renesas Technology America, Inc., All Rights Reserved 4 DMAC Features  4 or 8 channels — 2 or 4 with external triggering  4GB of address space  Transfers of up to 16,777,216 units  Byte, word, longword, and 16-byte data transfer units  Dual-and single-address modes  Processing of transfer requests from  External devices  On-chip peripherals –SCIF x 8 sources –IIC3 x 2 sources (supported by SH-2A only) –ADC x 2 sources –MTU2 x 5 sources –CMT x 2 sources (supported by SH-2A only)  Software (auto request)  Cycle-steal and burst-bus modes  Fixed and round-robin priority schemes  Interrupts after half or full data transfer

5. © 2008, Renesas Technology America, Inc., All Rights Reserved 5 Dual-Address Mode  Both source and destination are accessed by internal or external addresses  Two bus cycles are required for data transfer First bus cycle Second bus cycle

6. © 2008, Renesas Technology America, Inc., All Rights Reserved 6 Single-Address Mode  Both source and destination are external devices  One source is accessed by the DACK signal and the other by the address  Transfer can be performed in one cycle MCU

7. © 2008, Renesas Technology America, Inc., All Rights Reserved 7 Supported Data Transfers Notes: Dual = Dual-address mode; Single = Single address mode A 16-byte transfer is available only for on-chip peripherals that support longword access. DMAC Address Mode vs. Transfer Destination

9. © 2008, Renesas Technology America, Inc., All Rights Reserved 9 Channel Priority  When more than one DMAC channel is triggered, channel- priority modes determine the order of transfers.  DMAC has two channel priority modes:  Fixed –The priority among channels remains fixed –Two schemes are available:  Round robin –Priority changes after each unit is transferred –Channel of just-completed transfer moves to the position of lowest priority –Priority after reset: CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7 CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7 CH0 > CH4 > CH1 > CH5 > CH2 > CH6 > CH3 > CH7

10. © 2008, Renesas Technology America, Inc., All Rights Reserved 10 Bus Modes Cycle-steal mode  Normal –Upon completion of a transfer, the bus is given to another bus master (CPU, external bus request, etc.) –Bus released for 1 cycle  Intermittent (SH-2A series devices only) –Upon completion of a transfer, the bus is given to another bus master (CPU, external bus request, etc.) –Bus released for 16 or 64 cycles –DMAC occupies the bus less frequently Burst mode  Fastest way to transfer data  DMAC doesn’t release the bus until all requested transfers have been completed Two bus modes direct the use of the microcontroller’s buses

11. © 2008, Renesas Technology America, Inc., All Rights Reserved 11 Interrupt Controller  Controls interrupt requests to the CPU  Ascertains the priority of interrupt sources  Provides key features and functions  16 levels of priority  NMI noise-canceller function  /IRQOUT pin, which can signal the occurrence of an interrupt  Register bank interaction (in SH-2A devices) to save and restore CPU registers at high speed INTC Interrupt Source 4 Interrupt Source n Interrupt Source 3 Interrupt Source 2 Interrupt Source 1 CPU..

12. © 2008, Renesas Technology America, Inc., All Rights Reserved Exceptions and Interrupts  Exceptions are unusual and unexpected occurrences  Time and location generally cannot be predicted  Example is an Illegal instruction  Hardware offers methods to react, recover, and restart Exception sources include:  Resets  Address errors  Illegal instructions  TRAPA instructions Interrupt sources include:  NMI  User Break  External IRQ  On-chip peripherals  Interrupts are unusual occurrences that are expected to occur  Example is data-byte reception by a serial communications channel  CPU can launch a routine to handle the event

13. © 2008, Renesas Technology America, Inc., All Rights Reserved Interrupt Acceptance & Handling  INTC accepts interrupt requests according to priority  If interrupt request is accepted, interrupt handling process begins:  /IRQOUT driven low  Status Register pushed on stack and interrupt priority adjusted in CPU status register  Program counter pushed onto stack  /IRQOUT driven high  Address of interrupt service routine read from vector table  Interrupt service routine executed Stack R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 310 MQI3I2I1I0ST 310 Status Register GBR Global Base Register VBR Vector Base Register MAC H MAC Registers MAC L PR Procedure Register PC Program Counter Stack grows down Low Address High Address TBR Jump Table Base Register

14. © 2008, Renesas Technology America, Inc., All Rights Reserved 14 Interrupt Handling Flow

16. © 2008, Renesas Technology America, Inc., All Rights Reserved 16 SH-2 Series Interrupt Controller

17. © 2008, Renesas Technology America, Inc., All Rights Reserved 17 Number of States ______________________________________________ NMI, Peripheral ModuleIRQRemarks _____________________________________________________________________________________________________________________ DMAC/DTC active judgment 0 or 111 state required for interrupt signals for which DMAC/DTC activation is possible _____________________________________________________________________________________________________________________ Compare identified interrupt 23 priority with SR mask level _____________________________________________________________________________________________________________________ Wait for completion of X (≥ 0)The longest sequence is for interrupt or sequence currently being address-error processing (X = 4 + m1 + M2 + executed by CPUm3 + m4). If an interrupt-masking instruction follows, the time may be longer _____________________________________________________________________________________________________________________ Time from start of interrupt 5 + m1 + m2 + m3 exception processing until start of fetch of exception service routine’s first instruction _____________________________________________________________________________________________________________________ Interrupt total: 7 + m1 + m2 + m39 + m1 + m3 _________________________________________________________________________________________ Response, minimum: 1012 0.25µs to 0.3µs _________________________________________________________________________________________ Time, maximum: 12 + 2 (m1 + m2 + m3) + m4 13 + 2 (m1 + m2 + m3) + m4 0.48µs @ 40MHz _____________________________________________________________________________________________________________________ Note:m1 — m4 are the number of states needed for the following memory accesses: m1: SR save (longword); m2: PC save (longword write); m3: vector address read (longword write); m4: fetch first ISR instruction SH-2 Interrupt Response Time

19. © 2008, Renesas Technology America, Inc., All Rights Reserved 19 SH-2A Interrupt Controller

20. © 2008, Renesas Technology America, Inc., All Rights Reserved 20 SH-2A Register Banks  SH-2A CPU has 15 register banks, one for each interrupt priority  Register banks save and restore CPU register contents during interrupt handling  When bank is full and overflows, the stack can be used  SH-2A CPU can generate bank overflow and underflow exceptions

21. © 2008, Renesas Technology America, Inc., All Rights Reserved 21 SH-2A Interrupt Latency

22. © 2008, Renesas Technology America, Inc., All Rights Reserved 22 SH-2A Interrupt Response Times

23. © 2008, Renesas Technology America, Inc., All Rights Reserved Vector Table  Complete table contains entries for  Exception processing  Interrupt processing  Entries are always 32 bits wide and longword aligned  Vector table entries point to functions with no calling parameters and no return values  Vector base register provides a location base for the vector table that helps improve  Interrupt processing speed in ROM-less systems  Memory access in ROM monitor or bootloader applications Interrupt source Vector Vector table address offset Vector tables can be 0x400 bytes long!

24. © 2008, Renesas Technology America, Inc., All Rights Reserved  CPU reads initial values for PC and SP from exception vector table  Vector base register is initialized to 0x00000000  Interrupt mask bits of the SR are set to maximum (all interrupts masked)  Program execution begins at PC value read from exception vector table  Two reset types are supported:  Power-on reset –Reset vector from 0x00000000 –SP from 0x00000004  Manual reset (/RES=1, /MRES=0) –Reset vector from 0x00000008 –SP from 0x0000000C Exception Processing - Resets

25. © 2008, Renesas Technology America, Inc., All Rights Reserved Exception Processing-Instructions Exceptions can be triggered by instructions  TRAPA  General illegal (unimplemented) op-code  Illegal slots  General illegal instruction  Instruction that rewrites the PC

27. © 2008, Renesas Technology America, Inc., All Rights Reserved 27 Course Summary  Direct memory access controller  Interrupt controller