1. EE5900 Advanced VLSI Computer-Aided Design
Dr. Shiyan Hu
Office: EERC 731
Introduction
Adapted and modified from Digital Integrated Circuits: A Design Perspective
by Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic.

2. Class Time and Office Hour
EE141
Class Time and Office Hour
Class Time: MWF 14:05-14:55 (EERC 216)
Office Hours: MWF 15:00-15:50 or by appointment, office: EERC 731
Textbook (suggested)
Encyclopedia of Algorithms, M.-Y. Kao, Springer, 2008
Handbook of Algorithms for Physical Design Automation, Charles J. Alpert, Dinesh P. Mehta, Sachin S. Sapatnekar, CRC Press, 2008
Grading:
Homework 25%
Project %
Exams %

3. EE141
Course Website
Contact information of instructor
EERC 731
Instructor’s webpage:

4. EE141
Introduction
Why is designing digital ICs different today than it was before?
What is the challenge?

5. The Transistor Revolution
First transistor
Bell Labs, 1948

6. The First Integrated Circuit
First IC
Jack Kilby
Texas Instruments
1958

7. Intel 4004 Micro-Processor
EE141
Intel 4004 Micro-Processor
1971
1000 transistors
1 MHz operation

8. Intel 8080 Micro-Processor
1974
4500 transistors

9. Intel Pentium (IV) microprocessor
2000
42 million transistors
1.5 GHz

10. Not Only Microprocessors
Analog
Baseband
Digital Baseband
(DSP + MCU)
Power
Management
Small
Signal RF RF
Cell Phone
Digital Cellular Market
(Phones Shipped)
Units 48M 86M 162M 260M 435M
(data from Texas Instruments)

11. Many Chips 11

12. Basic Components In VLSI Circuits
Devices
Transistors
Logic gates and cells
Function blocks
Interconnects
Local interconnects
Global interconnects
Clock interconnects
Power/ground nets

13. Cross-Section of A Chip

14. CMOS transistors 3 terminals in CMOS transistors: G: Gate D: Drain
S: Source
nMOS transistor/switch X=1 switch closes (ON) X=0 switch opens (OFF)
pMOS transistor/switch X=1 switch opens (OFF) X=0 switch closes (ON)

15. An Example: CMOS Inverter
F = X’
+Vdd
GRD
F = X’ X
Logic symbol
Operation:
X=1  nMOS switch conducts (pMOS is open) and draws from GRD  F=0
X=0  pMOS switch conducts (nMOST is open) and draws from +Vdd  F=1
Transistor-level schematic

16. EE141
Moore’s Law
In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months.
He made a prediction that semiconductor technology will double its effectiveness every 18 months
Not true any more
Interconnect delay dominates
Variations

17. EE141
Moore’s Law
Electronics, April 19, 1965.

18. Transistor Counts 1 Billion Transistors K 1,000,000 100,000 10,000
EE141
Transistor Counts
1 Billion Transistors K
1,000,000
100,000
Pentium® III
10,000
Pentium® II
Pentium® Pro
1,000
Pentium®
i486
i386
100
80286 10
8086
Source: Intel 1
1975
1980
1985
1990
1995
2000
2005
2010
Projected
Courtesy, Intel

19. Moore’s law in Microprocessors
EE141
Moore’s law in Microprocessors
1000
2X growth in 1.96 years!
100 10 P6
Pentium® proc
Transistors (MT) 1
486
386
0.1
286
Transistors on Lead Microprocessors double every 2 years
8086
8085
0.01
8080
8008
4004
0.001
1970
1980
1990
2000
2010
Year
Courtesy, Intel

20. ITRS Prediction 20

21. Lead Microprocessors frequency doubles every 2 years
EE141
Frequency
10000
Doubles every 2 years
1000 P6
100
Pentium ® proc
Frequency (Mhz)
486 10
386
8085
8086
286 1
8080
8008
4004
0.1
1970
1980
1990
2000
2010
Year
Lead Microprocessors frequency doubles every 2 years
Courtesy, Intel

22. Lead Microprocessors power continues to increase
EE141
Power Dissipation
100 P6
Pentium ® proc 10
486
286
Power (Watts)
8086
386
8085 1
8080
8008
4004
0.1
1971
1974
1978
1985
1992
2000
Year
Lead Microprocessors power continues to increase
Courtesy, Intel

23. Power is a major problem
EE141
Power is a major problem
100000
18KW
5KW
10000
1.5KW
1000
500W
Pentium® proc
Power (Watts)
100
286
486
8086 10
386
8085
8080
8008 1
4004
0.1
1971
1974
1978
1985
1992
2000
2004
2008
Year
Power delivery and dissipation will be prohibitive
Courtesy, Intel

24. Power density too high to keep junctions at low temp
10000
Rocket
Nozzle
1000
Nuclear
Reactor
Power Density (W/cm2)
100
8086 10
Hot Plate
4004 P6
8008
8085
386
Pentium® proc
286
486
8080 1
1970
1980
1990
2000
2010
Year
Power density too high to keep junctions at low temp
Courtesy, Intel

25. Logic Design and Synthesis
VLSI Design Cycle
System Specification
e.g., Verilog
X=(AB*CD)+(A+D)+(A(B+C))
Y=(A(B+C))+AC+D+A(BC+D))
Functional Design
Logic Design and Synthesis

26. VLSI Design Cycle (cont.)
Physical Design
Fabrication
Packaging

27. Interconnects Dominate
300
250
200
Interconnect delay
150
Delay (psec)
100
Transistor/Gate delay 50 27
[CF] The problem is that at 0.18u and below interconnect overwhelmingly dominates the delay on a chip, and current design methods have been created to only consider the delay from the transistor gate. So, you never get a true timing picture of the performance of your chip during your design iterations. The impact of this is difficulty in achieving Design Closure. This is important because it will cause delay in the delivery of your chip and uncertainty in its performance.
[Michel] The above graphic shows how interconnect delay accounts for most of the delay in chips today and will continue to do so with advancing technologies. This is mainly due to the shrinking gate sizes which reduces the gate capacitance and the shrinking widths and spacing of the interconnect which increases the overall interconnect capacitance. Please turn to the next slide titled “and Coupling Dominates Interconnect”.
0.8
0.5
0.35
0.25
0.25
0.18
0.15
Technology generation (m)
Source: Gordon Moore, Chairman Emeritus, Intel Corp.

28. New Paradigm for VLSI Design
Interconnection
Transistors/Cells
Transistors/Cells
Interconnection
Conventional Approach
New Approach
Interconnect-Driven Design

29. Physical Design
Given a circuit after logic synthesis, to convert it into a layout (i.e., determine the physical location of each gate and the interconnects between gates). PD

30. Nanoscale Challenges Interconnect-limited designs Power barrier
Interconnect performance limitation
Interconnect modeling complexity
Interconnect reliability (signal integrity)
Power barrier
High degree of on-chip integration
Complexity and productivity
System on a chip
Variations

31. Robust Design For Variations
The difference between the designed value and the actual value
Robust design
Mitigate or compensate for variations
Robustness for lithography-induced variations

32. Chip Design and Fabrication
Fabricated Chip
Lithography Process
Designed Chip Layout 32

33. Photo-Lithography Process
Part of layout
optical
mask
oxidation
photoresist
photoresist coating
removal (ashing)
stepper exposure
Typical operations in a single
photolithographic cycle (from [Fullman]).
photoresist
development
acid etch
process
spin, rinse, dry
step 33

34. Lithography System 193nm wavelength Illumination 45nm features Mask
Objective Lens
Aperture
Wafer 34

35. What you design is NOT what you get!
Mask v.s. Printing
0.25µ
0.18µ
0.13µ
90-nm
65-nm
Layout
What you design is NOT what you get! 35

36. Tolerable variation (nm)
Motivation
Chip design cannot be fabricated
Gap
Lithography technology: 193nm wavelength
VLSI technology: 45nm features
Lithography induced variations
Impact on timing and power
Even for 180nm technology, variations up to 20x in leakage power and 30% in frequency were reported.
Technology node
130nm
90nm
65nm
45nm
Gate length (nm)
Tolerable variation (nm) 90
5.3 53
3.75 35
2.5 28 2
Wavelength (nm)
248
193 36 36

37. Gap: Lithography Tech. v.s. VLSI Tech.
28nm, tolerable distortion: 2nm
193nm
Increasing gap  Printability problem (and thus variations) more severe! 37

38. EE141
Summary
Digital integrated circuit design challenges in nanoscale regime
High speed
Low power
Short design time for highly complex circuit having 1 billion transistors
Reliable under variations