1. Accellera Systems Initiative Update Dennis Brophy, Vice Chair | April 9, 2012

2. 2 Thanks to Our Global Sponsors © 2012 Accellera Systems Initiative, Inc.

3. April 9, 2012 Accellera and OSCI Merge “Our new organization will leverage the excellent work of our technical committees to provide a bigger benefit to the electronics industry. By forming a combined organization, we will be able to accelerate development of system level standards that will move electronic design productivity to the next level.” Shishpal Rawat, Accellera Systems Initiative Chair 3

4. © 2012 Accellera Systems Initiative, Inc. April 9, 2012 Accellera Systems Initiative Our Mission  To provide design and verification standards required by systems, semiconductor, IP and design tool companies to enhance a front-end design automation process.  To collaborate with its community of companies, individuals and organizations in delivering the standards that lower the cost to design commercial EDA, IC and embedded system solutions. 4

5. © 2012 Accellera Systems Initiative, Inc. April 9, 2012 Merger Update  Integration of Accellera and OSCI Organizations - WIP -Ongoing review of operational procedures and policies -Leveraging strengths from both organizations to expand applicability and increase adoption -Focused on next generation of EDA and IP standards  Continue to providing free downloads of IEEE standards -IEEE 1666 SystemC available since mid-January -IEEE 1685 IP-XACT downloads going strong  New Technical Excellence Award Program Launched -Candidates peer-nominated from across the organization -Recognizes work by people across multiple Accellera Systems Initiative standards 5

6. © 2012 Accellera Systems Initiative, Inc. April 9, 2012 Accellera Systems Initiative - Integration  Organizational Structure in Review -Procedures and Policies -IP Rights -Web Infrastructure, User forums  Expanding DVCon as “the” premier conference addressing functional design and verification -Accellera Systems Initiative Day Monday Feb. 27 th -Full conference registration & Monday tutorial attendance up from last year  Expanding Global Sponsorship Program -Opportunity for multiple companies to co-sponsor our events -Videos of all DVCon Monday tutorials and NASCUG meeting will be available on www.accellera.org 6

7. © 2012 Accellera Systems Initiative, Inc. April 9, 2012 IEEE 1666 SystemC Downloads 7 47,165 downloads of IEEE1666-2005 through January 2012 5,158 downloads of IEEE1666-2011 from January 11 through March 31 http://standards.ieee.org/getieee/1666/download/ 1666-2011.pdf

8. © 2012 Accellera Systems Initiative, Inc. April 9, 2012 IEEE 1685 IP-XACT Downloads 8 http://standards.ieee.org/getieee/1685/download/ 1685-2009.pdf

9. 2012 Technical Excellence Award John Aynsley  For his dedication to the SystemC language and community.  His contributions span the full range of SystemC language, transaction-level modeling and configuration.  Instrumental in the various working groups converging on technically sound solutions. 9

10. © 2011-2012 Accellera Systems Initiative, Inc. Also known as… 10

11. © 2012 Accellera Systems Initiative, Inc. April 9, 2012 SystemC Users Scope Expands  Unified Coverage Interoperability Standard  Universal Verification Methodology (UVM) 2.0  Verilog and SystemC Analog/Mixed-Signal (AMS)  IP-XACT and System RDL 11

12. © 2012 Accellera Systems Initiative, Inc. April 9, 2012 SystemC AMS 2.0 Draft Standard Now Open for Public Review  Standard addresses dynamic and reactive mixed-signal system design  Language Reference Manual available for public review at accellera.org accellera.org  Draft features additional semantics and language constructs and introduces dynamic features to the Timed Data Flow (TDF) -model of computation -abstract modeling style introduced in SystemC AMS  Review open until April 30, 2012 12

13. 13 John Aynsley, Doulos; Michael McNamara, Cadence; Michael Meredith, Forte And More! Available at: http://www.accellera.org/news/videos/ TLM-2.0 Standard and Synthesizable Subset TLM-2.0 in Action: An Example-based Approach to TLM and the New World of Model Interoperability John Aynsley, Doulos; David Black, XtremeEDA Zhu Zhou, Intel; Frank Schirrmeister, Synopsys John Aynsley, Doulos Using TLM Extensions for Bus Locking and Snooping Technical Video Tutorials Available Online

14. © 2012 Accellera Systems Initiative, Inc. April 9, 2012 Summary  Organizational Structure Refinement in Progress  Standards Unite Under One Roof! Expanded Scope for all in Combined Organization -Unified Coverage Interoperability Standard -Universal Verification Methodology (UVM) 2.0 -Verilog and SystemC Analog/Mixed-Signal (AMS) -IP-XACT and System RDL  SystemC AMS 2.0 Draft Standard Now Open for Public Review -Share your feedback!  Technical Tutorials and Users Presentations Available Online at no cost to users www.accellera.org 14

15. © 2012 Accellera Systems Initiative, Inc. April 9, 2012 Backup 15

16. © 2012 Accellera Systems Initiative, Inc. April 9, 2012 Accellera Systems Initiative Supported IEEE Working Groups 1800 SystemVerilog Karen Pieper Tabula 1801 UPF John Biggs ARM 1076 VHDL Jim Lewis SynthWorks 1666 SystemC Stan Krolikoski Cadence SystemC TLM Bart Vanthournout Synopsys SystemC AMS Martin Barnasconi NXP SystemC CCI Trevor Wieman Intel IP-XACT Rohit Jindal STMicrosystems VIP Hillel Miller Freescale Tom Alsop Intel IP Tagging Kathy Werner Freescale Technical Committee Karen Pieper, Tabula Board of Directors Shishpal Rawat, Intel Marketing Committee Thomas Li, Springsoft Administration SystemC Language David Black Doulos SystemC Synthesis Andres Takach Calypto UCIS Richard Ho DE Shaw OVL Kenneth Larson Mentor Graphics Verilog-AMS Sri Chandra Freescale Interface (ITC)‏ Brian Bailey EDA DesignLine 16

17. © 2011-2012 Accellera Systems Initiative, Inc. Verification Intellectual Property (VIP) Universal Verification Methodology (UVM) 1.1 Open Verification Library (OVL) 2.6 Verilog-AMS (V-AMS) 2.3.1 Standard Co-Emulation Modeling Interface (SCE-MI) 2.1 Unified Coverage Interoperability Standard (UCIS) 1.0 (imminent) IP-XACT (Q1 2012) Intellectual Property (IP) Tagging (launched) SystemC Synthesizable Subset Draft 1.3 SystemC Analog Mixed-Signal (AMS) 1.0 SystemC Configuration, Control & Inspection (CCI Requirements) SystemC Language Standard Transaction Level Modeling (TLM) 1.0 and 2.0 Open Source Companions: - UVM Reference Implementation 1.1 - SystemC Proof of Concept Library (POCL) - SystemC Verification Library 1.0p2 Current Standards 9 th Annual DVCon – Our flagship conference Ongoing Technical Activities 17

18. © 2012 Accellera Systems Initiative, Inc. April 9, 2012 Acronyms & Definitions  AMS: Analog/Mixed Signal  CCI: Configuration, Control & Inspection  DVCon: Design & Verification Conference  EDA: Electronic Design Automation  GET: Free IEEE LRM download program  IC: Integrated Circuit  IP: Intellectual Property  IPR: Intellectual Property Rights  IP-XACT : Metadata standard for IP integration  IEEE : Institute of Electrical and Electronics Engineers  ITC: Interface Technical Committee  LWG: Language Working Group  OCI: Open Compression Interface  OSCI: Open SystemC Initiative  OVI: Open Verilog International  OVL : Open Verification Library  PSL: Property Specification Language  SDF: Standard Delay Format  SC: SystemC  SCV: SystemC Verification  SPIRIT: Structure for Packaging, Integrating, and Reusing IP within Tool-flows  SV: SystemVerilog  SWG: Synthesis Working Group  TLM: Transaction-Level Modeling  UCIS: Unified Coverage Interoperability Standard  UPF: Unified Power Format  UVM: Universal Verification Methodology  V-AMS: Verilog-Analog/Mixed Signal  VHDL: VHSIC Hardware Description Language  VI: VHDL International  VIP: Verification Intellectual Property 18