1. Transistor and Circuit Design for 100-200 GHz ICs rodwell@ece.ucsb.edu 805-893-3244, 805-893-5705 fax Mark Rodwell University of California, Santa Barbara V. Paidi, Z. Griffith, D. Scott, Y. Dong, M. Dahlström, Y. Wei, N. Parthasarathy University of California, Santa Barbara Lorene Samoska, Andy Fung Jet Propulsion Laboratories M. Urteaga, R. Pierson, P. Rowell, B. Brar Rockwell Scientific Company S. Lee, N. Nguyen, and C. Nguyen Global Communication Semiconductors 2004 IEEE Compound Semiconductor IC Symposium, October, Monterey

2. Potential applications for 100-300 GHz Electronics Optical Fiber Transmission 40 Gb/s: InP and SiGe ICs commercially available 80 & 160 Gb/s is feasible 80-160 Gb/s InP ICs now clearly feasible ~100 GHz modulators demonstrated (KTH Stockholm) 100 + GHz photodiodes demonstrated in 1980's challenge: limit to range due to fiber dispersion challenge: competition with WDM using 10 Gb CMOS ICs Radio-wave Transmission / Radar / Imaging 65-80 GHz, 120-160 GHz, 220-300 GHz 100 Gb/s transmission over 1 km in heavy rain 300 GHz imaging for foul-weather aviation science spectroscopy, radio astronomy Mixed-Signal ICs for Military Radar/Comms direct digital frequency synthesis, ADCs, DACs high resolution at very high bandwidths sought 40 Gb/s InP HBT fiber chip set (Gtran Inc.) 100 Gb/s over 1 km in heavy rain : 250 GHz carrier 300 GHz imagining radar for foul-weather aviation

3. Fast IC Technologies InP HBT: Advantages 3.5x10 7 cm/s collector velocity 500 Ohm/square base sheet  Performance 500 nm scaling generation: 400 GHz f  / 500 GHz f max 4 V breakdown 150 GHz static dividers 178 GHz amplifiers Comments scaling will improve bandwidth scaling can reduce power small market high cost SiGe HBT: Advantages superior scaling extrinsic parasitic reduction CMOS integration Performance 130 nm scaling generation: 210 GHz f  / 270GHz f max 96 GHz static dividers 77 GHz amplifiers 150 GHz push-push VCO- 75 GHz fundamental SOI CMOS: Advantages cost, power, integration scales Performance 90 nm scaling generation: ~200 GHz f  & f max 60 GHz 2:1 mux 91 GHz amplifiers

4. Optical Transmitters / Receivers are Mixed-Signal ICs TIA: small-signal LIA: often limiting MUX/CMU & DMUX/CDR: mostly digital Small-signal cutoff frequencies (f t, f max ) are ~ predictive of analog speed Limiting and digital speed much more strongly determined by I /C ratios

5. We design HBTs for low gate delay, not for high f  & f max

6. Why isn't base+collector transit time so important for logic? Depletion capacitances present over full voltage swing, no large-signal reduction

7. Scaling Laws, Collector Current Density, C cb charging time Collector Field Collapse (Kirk Effect) Collector Depletion Layer Collapse 0 mA/  m 2 10 mA/  m 2 0 mA/  m 2 10 mA/  m 2 GaAsSb base InGaAs base Collector capacitance charging time scales linearly with collector thickness if J = J max

8.   ex  7  m 2 needed for 200 GHz clock rate ECL delay not well correlated with f  or f max Key HBT Scaling Limit  Emitter Resistance Largest delay is charging C cb  J e  10 mA/  m 2 needed for 200 GHz clock rate Voltage drop of emitter resistance becomes excessive R ex I c =  ex J e = (15  m 2 )  (10 mA/  m 2 ) = 150 mV  considerable fraction of  V logic  300 mV Degrades logic noise margin

9. Breakdown: Thermal failure is more significant than BVCEO Low thermal resistance is critical. DHBTs are superior to SHBTs.

10. Bipolar Transistor Scaling Laws & Scaling Roadmaps key device parameterrequired change collector depletion layer thicknessdecrease 2:1 base thicknessdecrease 1.414:1 emitter junction widthdecrease 4:1 collector junction widthdecrease 4:1 emitter resistance per unit emitter areadecrease 4:1 current densityincrease 4:1 base contact resistivity (if contacts lie above collector junction) decrease 4:1 base contact resistivity (if contacts do not lie above collector junction) unchanged Scaling Laws: design changes required to double transistor bandwidth InP Technology Roadmap 40 / 80 / 160 Gb/s digital clock rate Key scaling challenges emitter & base contact resistivity current density→ device heating collector-base junction width scaling & Yeild ! key figures of merit for logic speed

11. InP DHBTs: 600 nm emitter width, 150 nm thick collector 391 GHz f , 505 GHz f max Zach Griffith setback grade base emitter InP collector C cb /I c ~0.5 ps/V

12. +V 0V kzkz Microstrip mode Substrate modes +V 0V CPW mode 0V CPW has parasitic modes, coupling from poor ground plane integrity kzkz Microstrip has high via inductance, has mode coupling unless substrate is thin. We prefer (credit to NTT) thin-film microstrip wiring, inverted is best for complex ICs -V0V+V 0V Slot mode ground straps suppress slot mode, but multiple ground breaks in complex ICs produce ground return inductance ground vias suppress microstrip mode, wafer thinning suppresses substrate modes M. Urteaga, Z. Griffith, S. Krishnan

13. units data current steering data emitter followers clock current steering clock emitter followers size m2m2 0.5 x 3.50.5 x 4.5 0.5 x 5.5 current density mA/  m 2 6.94.4 C cb /I c psec / V 0.590.990.740.86 V cb V 0.60 1.7 ff GHz 301260301280 f max GHz 358268358280 UCSB / RSC / GCS 150 GHz Static Frequency Dividers IC design: Zach Griffith, UCSB HBT design: RSC / UCSB / GCS IC Process / Fabrication: GCS Test: UCSB / RSC / Mayo probe station chuck @ 25  C P DC,total = 659.8 mW divider core without output buffer  594.7 mW

14. UCSB 142 GHz Master-Slave Latches (Static Frequency Dividers) Static 2:1 divider: Standard digital benchmark. Master-slave latch with inverting feedback. Performance comparison between digital technologies UCSB technology 2004: InP mesa HBT technology 12-mask process 600 nm emitter width 142 GHz maximum clock. Implications: 160 Gb/s fiber ICs 100 + Gb/s serial links Target is 260 GHz clock rate at 300 nm scaling generation Z. Griffith, M. Dahlström 25 o C

15. Reducing Divide-by-2 Dissipation ECL with impedance-matched 50 Ohm bus: 25 Ohm load→ switch 12 mA 12 mA x 7 x 4 V = 336 mW/latch CML with impedance-matched 50 Ohm bus: 25 Ohm load→ switch 12 mA 12 mA x 3 x 3 V = 108 mW/latch Low-Power CML 100 Ohm loaded → switch 3 mA 3 mA x 3 x 3 V = 27 mW/latch What parts of circuit are included in stated dissipation ? 12 mA 50 Ohm bus50 Ohm 12 mA 50 Ohm bus50 Ohm 50 Ohm bus100 Ohm 3 mA

16. 7.5 mW output power Mesa DHBT Power Amplifiers for 100-200 GHz Communications 7 dB gain measured @ 175 GHz 175 GHz Power Amplifier Demonstrated in a 300 GHz fmax process 500 GHz fmax DHBTs available now, 600 GHz should be feasible soon → feasibility of power amplifiers to 350 GHz → Ultra high frequency communications 2 fingers x 0.8 um x 12 um, ~250 GHz f , 300 GHz f max, V br ~ 7V, ~ 3 mA/um 2 current density V. Paidi, Z. Griffith, M. Dahlström

17. 172 GHz Common-Base Power Amplifier 8.3 dBm saturated output power 4.5-dB associated power gain at 172 GHz DC bias: Ic=47 mA, Vcb=2.1V. V. Paidi, Z. Griffith, M. Dahlström 6 dB gain

18. 176 GHz Two-Stage Amplifier 7-dB gain at 176 GHz 8.1 dBm output power, 6.3 dB power gain at 176 GHz 9.1 dBm saturated output power at 176 GHz V. Paidi, Z. Griffith, M. Dahlström

19. InP HBT limits to yield: non-planar process Yield quickly degrades as emitters are scaled to submicron dimensions Griffith, Dahlström

20. Parasitic Reduction for Improved InP HBT Bandwidth SiO 2 P base N+ subcollector N- thick extrinsic base : low resistance thin intrinsic base: low transit time wide emitter contact: low resistance narrow emitter junction: scaling (low R bb /A e ) wide base contacts: low resistance narrow collector junction: low capacitance At a given scaling generation, intelligent choice of device geometry reduces extrinsic parasitics Much more fully developed in Si… These are planar approximations to radial contacts: extrinsic base extrinsic emitter N+ subcollector extrinsic base → greatly reduced access resistance

21. UCSB/RSC/GCS TFAST HBT Technology Development High performance, low yield technology Difficult to scale to W E < 0.4 um Processed for epitaxy and circuit validation Scaled mesa-HBT S3 Technology Improved base-emitter process flow Process scalable to W E < 0.25 um Process modules that can be added to HBT technology Emitter regrowth for high yield, low Re Extrinsic base for low R bb Pedestal implant for reduced Ccb Allows continued scaling even if base & emitter contact resistivities do not improve. Regrowth Technology S.I. InP N + Subcollector N - collector extrinsic base base contact regrown emitter emitter contact Si x N y collector contact intrinsic base

22. Low Parasitic, Scalable HBT processes Collector pedestal implantExtrinsic emitter regrowthEmitter sidewall process high-yield (10,000 transistor) alternative to emitter-base definition by mesa etch SiGe-like emitter-base process wide emitter contact → low resistance thick extrinsic base → low resistance Independent control of base contact & collector junction widths → reduced capacitance Miguel Urteaga Dennis Scott, Yun Wei RSC/GCS/UCSB Vitesse similar to earlier Hitachi, NEC, NTT GaAs HBT processes RSC/GCS/UCSB Northrup Grumman RSC/GCS/UCSB HRL Labs Yingda Dong

23. Collector Pedestal Implant for InP HBTs Pedestal can be integrated into: sidewall or mesa emitter processes, emitter regrowth process ~2:1 reduction in collector base capacitance Good DC characteristics, high power density, increased breakdown: 5.4 V with a 90 nm thick collector N ++ InP subcollector Collector contact N + pedestal Base contact Emitter contact SI substrate N - collectorUID InP large collector capacitance reduction significant increase in breakdown 2(10 13 ) V-sec Johnson Figure-of-Merit transistors have low leakage, good DC characteristics Y. Dong et. al.: ISDRC December 2003, DRC June 2004

24. What's next ? 250 nm Scaling Generation for >200 GHz clock sidewall processes for 300 nm at high yield narrow collector junctions needed low contact resistivity modified sidewall spacer process &/or collector pedestal power density near reliability limits narrow emitters should improve heatsinking Decreasing A collector /A emitter decreases required J e eases thermal design

25. Indium Phosphide HBTs for 100-200 GHz ICs InP HBT: high speed & room left to scale 150 GHz digital clock (static divider) at 500 nm scaling generation 210 GHz clock should soon be feasible at 250 nm scaling. low NRE; low mask cost Applications feasible soon: 160 Gb fiber ICs, 300 GHz MIMICs for communications & radar GHz mixed-signal ICs for radar & communications Planar processes address yield limitations emitter-base junction: liftoff-free dielectric sidewall process base-collector junction: planar implanted process Volume markets are needed to drive down cost GaAs HBT power amplifier processes are cheap Why can't InP HBT be inexpensive ? InP HBT can be scaled at high yield Key to survival of the technology are emergence of singificant markets progress relative to CMOS & InP